Chapter 3: Transmitter - Xilinx Virtex UltraScale+ FPGAs User Manual

Transmitter
This chapter shows how to configure and use each of the functional blocks inside the transmitter
(TX). Each transceiver includes an independent transmitter, which consist of a PCS and a PMA.
The following figure shows the functional blocks of the transmitter. Parallel data flows from the
device logic into the TX interface through the PCS and PMA, and then out the TX driver as high-
speed serial data.
TX
Pre/
TX PIS
Pre2/
Driver
O
Post
Emp
TX PMA
The key elements within the GTM transceiver TX are:
1. TX Interface
2. TX FEC
3. TX Buffer
4. TX Pattern Generator
5. TX Polarity Control
6. TX Gray Encoder
7. TX Pre-Coder
8. TX Fabric Clock Output Control
9. TX Configurable Driver
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
GTM Transceiver TX Block Diagram
Figure 24:
Pre- Gray
Polarity
Coder Encoder
TX PCS
To RX Parallel
Data (Near-End
PCS Loopback)

Chapter 3: Transmitter

Pattern
Generator
FIFO FEC
Send Feedback
Chapter 3
TX
Interface
From RX Parallel
Data (Far-End
PCS Loopback)
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