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Operational Details
Any time a packet with a PCR is received, the timestamp for that packet is
compared with the PCR value in software. A PLL is implemented in software
to synchronize the STCLK with the system time clock. The DSP updates the
VIC input register (VICIN) using the output from this algorithm, which in turn
drives the VCTL output that controls the system time clock VCXO.
If f is the frequency of PCRs in the incoming bit stream, the interpolation rate
R of the VCTL output is given in Equation 6–1, where k is determined by the
precision
Equation 6–1. Relationship Between Interpolation Rate and Input Frequency
Equation 6–2 gives the relation between k and the precision .
Equation 6–2. Relationship of Frequency Multiplier to Precision
Table 6–2 gives some k and R values for different 's with f fixed at 40 kHz.
Once a suitable interpolation frequency is determined, the clock divider can
be set.
Table 6–2. Example Values for Interpolation Rate
6-4
VCXO Interpolated Control Port
specified by you.
k u (
k
R
9
96.0
3.8 MHz
10
151.0
6.0 MHz
11
240.0
9.6 MHz
12
381.0
15.2 MHz
13
605.0
24.2 MHz
14
960.0
38.4 MHz
15
1523.0
60.9 MHz
16
2418.0
96.7 MHz
R + kf
3
(p
2
(2
b
* 1)
2
) 3)
SPRU629
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