Video Display Field 1 Vertical Synchronization End Register (Vdvsyne1) - Texas Instruments TMS320C64x DSP Reference Manual

Video Display Registers

4.12.18 Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1)

The video display field 1 vertical synchronization end register (VDVSYNE1)
controls the end of vertical synchronization in field 1. The VDVSYNE1 is
shown in Figure 4–56 and described in Table 4–23.
Generation of the vertical synchronization is shown in Figure 4–6, page 4-7.
The VSYNC signal is deasserted whenever the frame line counter (FLCOUNT)
is equal to VSYNCYSTOP1 and the frame pixel counter (FPCOUNT) is equal
to VSYNCXSTOP1.
Figure 4–56. Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1)
31 28 27
Reserved
R-0
15 12 11
Reserved
R-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 4–23. Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1)
Field Descriptions
†
Bit field
31–28 Reserved
27–16 VSYNCYSTOP1
15–12 Reserved
11–0 VSYNCXSTOP1
† For CSL implementation, use the notation VP_VDVSYNE1_field_symval
4-80 Video Display Port
†
symval Value
– 0 Reserved. The reserved bit location is always read as
0. A value written to this field has no effect.
OF(value) 0–FFFh Specifies the line where VSYNC is deasserted for
field 1.
– 0 Reserved. The reserved bit location is always read as
0. A value written to this field has no effect.
OF(value) 0–FFFh Specifies the pixel where VSYNC is deasserted in
field 1.
VSYNCYSTOP1
R/W-0
VSYNCXSTOP1
R/W-0
Description
16
0
SPRU629