Sign In
Upload
Manuals
Brands
Texas Instruments Manuals
Signal Processors
TMS320VC5501
Texas Instruments TMS320VC5501 Manuals
Manuals and User Guides for Texas Instruments TMS320VC5501. We have
2
Texas Instruments TMS320VC5501 manuals available for free PDF download: Reference Manual, Instruction Cache
Texas Instruments TMS320VC5501 Reference Manual (285 pages)
DSP, Multichannel Buffered Serial Port (McBSP)
Brand:
Texas Instruments
| Category:
Signal Processors
| Size: 1.35 MB
Table of Contents
Table of Contents
6
Figures
12
Introduction to the Mcbsp
19
Introduction
19
Key Features of the Mcbsp
19
Block Diagram of the Mcbsp
21
Conceptual Block Diagram of the Mcbsp
21
CLKR Pin
21
Mcbsp Pins
23
Mcbsp Operation
25
Data Transfer Process of a Mcbsp
25
Data Transfer Process for Word Length of 8, 12, or 16 Bits
25
Mcbsp Data Transfer Paths
25
Data Transfer Process for Word Length of 20, 24, or 32 Bits
26
Companding (Compressing and Expanding) Data
27
Companding Formats
27
Companding Processes
27
Capability to Compand Internal Data
28
Μ-Law Transmit Data Companding Format
28
A-Law Transmit Data Companding Format
28
Reversing Bit Order: Option to Transfer LSB First
29
Two Methods by Which the Mcbsp Can Compand Internal Data
29
Clocking and Framing Data
30
Clocking
30
Serial Words
30
Frames and Frame Synchronization
31
Detecting Frame-Sync Pulses, Even in the Reset State
32
Ignoring Unexpected Frame-Sync Pulses
32
Frame Frequency
32
Maximum Frame Frequency
32
Mcbsp Operating at Maximum Packet Frequency
33
Frame Phases
34
Number of Phases, Words, and Bits Per Frame
34
Single-Phase Frame Example
34
Mcbsp Register Bits that Determine the Number of Phases, Words, and Bits Per Frame
34
Dual-Phase Frame Example
35
Single-Phase Frame for a Mcbsp Data Transfer
35
Dual-Phase Frame for a Mcbsp Data Transfer
35
Implementing the AC97 Standard with a Dual-Phase Frame
36
Timing of an AC97-Standard Data Transfer Near Frame Synchronization
37
Mcbsp Reception
38
Mcbsp Reception Physical Data Path
38
Mcbsp Reception Signal Activity
38
Mcbsp Transmission Physical Data Path
40
Mcbsp Transmission Signal Activity
40
Interrupts and DMA Events Generated by a Mcbsp
42
Chapter 3 Sample Rate Generator of the Mcbsp
44
Conceptual Block Diagram of the Sample Rate Generator
45
Sample Rate Generator
45
Clock Generation in the Sample Rate Generator
47
Effects of DLB and CLKSTP on Clock Modes
47
Choosing an Input Clock for the Sample Rate Generator with the SCLKME and
48
Possible Inputs to the Sample Rate Generator and the Polarity Bits
49
Falling Edge
50
Polarity Options for the Input to the Sample Rate Generator
50
Frame Sync Generation in the Sample Rate Generator
52
Synchronizing Sample Rate Generator Outputs to an External Clock
53
CLKG Synchronization and FSG Generation When GSYNC = 1, CLKGDV = 1, and CLKS Provides the Sample Rate Generator Input Clock
54
CLKG Synchronization and FSG Generation When GSYNC = 1, CLKGDV = 3, and CLKS Provides the Sample Rate Generator Input Clock
54
Reset and Initialization Procedure for the Sample Rate Generator
55
Sample Rate Generator Clocking Examples
57
ST-BUS and MVIP Clocking Example
57
Single-Rate Clock Example
58
Double-Rate Clock Example
59
Chapter 4 Mcbsp Exception/Error Conditions
60
Mcbsp Exception/Error Conditions
61
Overrun in the Receiver
62
Overrun in the Mcbsp Receiver
63
Overrun Prevented in the Mcbsp Receiver
63
Unexpected Receive Frame-Sync Pulse
64
An Unexpected Frame-Sync Pulse During a Mcbsp Reception
66
Proper Positioning of Frame-Sync Pulses
66
Data in the Mcbsp Transmitter Overwritten And, Therefore, Not Transmitted
67
Overwrite in the Transmitter
67
Underflow in the Transmitter
68
Underflow During Mcbsp Transmission
69
Underflow Prevented in the Mcbsp Transmitter
69
Possible Responses to Transmit Frame-Sync Pulses
70
Unexpected Transmit Frame-Sync Pulse
70
An Unexpected Frame-Sync Pulse During a Mcbsp Transmission
72
Proper Positioning of Frame-Sync Pulses
72
Chapter 5 Multichannel Selection Modes
74
Configuring a Frame for Multichannel Selection
77
Selection Mode
78
Using Two Partitions
78
Alternating between the Channels of Partition a and the Channels of Partition B
79
Reassigning Channel Blocks Throughout a Mcbsp Data Transfer
80
Receive Channel Assignment and Control When Eight Receive Partitions Are Used
81
Mcbsp Data Transfer in the 8-Partition Mode
82
Transmit Channel Assignment and Control When Eight Transmit Partitions Are Used
82
Multichannel Selection
77
Receive Multichannel Selection Mode
83
Selecting a Transmit Multichannel Selection Mode with the XMCM Bits
84
Transmit Multichannel Selection Mode
84
Activity on Mcbsp Pins for the Possible Values of XMCM
86
Using Interrupts between Block Transfers
88
Typical SPI Interface
91
Bits Used to Enable and Configure the Clock Stop Mode
93
Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme
94
SPI Transfer with CLKSTP = 10B (no Clock Delay), CLKXP = 0, CLKRP
95
SPI Transfer with CLKSTP = 11B (Clock Delay), CLKXP = 0, CLKRP
95
SPI Transfer with CLKSTP = 10B (no Clock Delay), CLKXP = 1, CLKRP
96
SPI Transfer with CLKSTP = 11B (Clock Delay), CLKXP = 1, CLKRP
96
Mcbsp as the SPI Master
99
Bit Values Required to Configure the Mcbsp as an SPI Master
100
Mcbsp as an SPI Slave
102
Bit Values Required to Configure the Mcbsp as an SPI Slave
103
Register Bits Used to Reset or Enable the Mcbsp Receiver
109
Reset State of each Mcbsp Pin
110
Register Bit Used to Set Receiver Pins to Operate as Mcbsp Pins
111
Register Bit Used to Enable/Disable the Digital Loopback Mode
112
Receive Signals Connected to Transmit Signals in Digital Loopback Mode
112
Register Bits Used to Enable/Disable the Clock Stop Mode
113
Register Bit Used to Enable/Disable the Receive Multichannel Selection Mode
114
Register Bit Used to Choose One or Two Phases for the Receive Frame
115
Register Bits Used to Set the Receive Word Length(S)
116
Register Bits Used to Set the Receive Frame Length
118
How to Calculate the Length of the Receive Frame
119
Register Bit Used to Enable/Disable the Receive Frame-Sync Ignore Function
120
Register Bits Used to Set the Receive Companding Mode
121
Register Bits Used to Set the Receive Data Delay
122
Range of Programmable Data Delay
123
Register Bits Used to Set the Receive Sign-Extension and Justification Mode
125
Example: Use of RJUST Field with 12-Bit Data Value 0Xabc
125
Example: Use of RJUST Field with 20-Bit Data Value 0Xabcde
126
Register Bits Used to Set the Receive Interrupt Mode
127
Register Bits Used to Set the Receive Frame Sync Mode
128
The Effect on the FSR Pin
130
Register Bit Used to Set Receive Frame-Sync Polarity
131
Data Clocked Externally Using a Rising Edge and Sampled by the Mcbsp Receiver on a
133
Register Bits Used to Set the SRG Frame-Sync Period and Pulse Width
134
Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods
135
Register Bits Used to Set the Receive Clock Mode
136
Register Bit Used to Set Receive Clock Polarity
139
Data Clocked Externally Using a Rising Edge and Sampled by the Mcbsp Receiver on a
141
Register Bits Used to Set the Sample Rate Generator (SRG) Clock
142
Register Bit Used to Set the SRG Clock Synchronization Mode
144
Register Bits Used to Set the SRG Clock Mode (Choose an Input Clock)
145
Falling Edge
146
Register Bits Used to Set the SRG Input Clock Polarity
146
Register Bits Used to Place Transmitter in Reset
151
Reset State of each Mcbsp Pin
152
Register Bit Used to Set Transmitter Pins to Operate as Mcbsp Pins
153
Register Bits Used to Enable/Disable the Clock Stop Mode
155
Register Bits Used to Enable/Disable Transmit Multichannel Selection
156
Register Bit Used to Choose One or Two Phases for the Transmit Frame
157
Register Bits Used to Set the Transmit Word Length(S)
158
Register Bits Used to Set the Transmit Frame Length
160
How to Calculate Frame Length
161
Register Bit Used to Enable/Disable the Transmit Frame-Sync Ignore Function
162
Register Bits Used to Set the Transmit Companding Mode
163
Register Bits Used to Set the Transmit Data Delay
164
Range of Programmable Data Delay
165
Register Bit Used to Set the Transmit DXENA (DX Delay Enabler) Mode
167
DX Delay When DXENA
167
Register Bits Used to Set the Transmit Interrupt Mode
168
Register Bits Used to Set the Transmit Frame-Sync Mode
169
How FSXM and FSGM Select the Source of Transmit Frame-Sync Pulses
170
Register Bit Used to Set Transmit Frame-Sync Polarity
171
Data Clocked Externally Using a Rising Edge and Sampled by the Mcbsp Receiver on a
173
Register Bits Used to Set the SRG Frame-Sync Period and Pulse Width
174
Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods
175
Register Bit Used to Set the Transmit Clock Mode
176
How the CLKXM Bit Selects the Transmit Clock and the Corresponding Status
176
Register Bit Used to Set Transmit Clock Polarity
178
Register Bits Used to Set the Sample Rate Generator (SRG) Clock
181
Register Bit Used to Set the SRG Clock Synchronization Mode
183
Register Bits Used to Set the SRG Clock Mode (Choose an Input Clock)
184
Register Bits Used to Set the SRG Input Clock Polarity
185
Register Bits Used to Set the SRG Input Clock Polarity
186
How to Use Mcbsp Pins for General-Purpose I/O
190
Mcbsp Emulation Modes Selectable with the FREE and SOFT Bits of SPCR2
193
Reset State of each Mcbsp Pin
196
Four 8-Bit Data Words Transferred To/From the Mcbsp
203
One 32-Bit Data Word Transferred To/From the Mcbsp
204
Data Receive Registers (DRR1 and DRR2)
209
Data Transmit Registers (DXR1 and DXR2)
210
SPCR1 Bit Descriptions
212
SPCR2 Bit Descriptions
216
Receive Control Registers (RCR1 and RCR2)
220
RCR1 Bit Descriptions
221
RCR2 Bit Descriptions
223
Transmit Control Registers (XCR1 and XCR2)
226
XCR1 Bit Descriptions
227
XCR2 Bit Descriptions
229
Sample Rate Generator Registers (SRGR1 and SRGR2)
232
SRGR1 Bit Descriptions
233
Divide-Down Value
234
SRGR2 Bit Descriptions
235
Multichannel Control Registers (MCR1 and MCR2)
238
MCR1 Bit Descriptions
239
Pin Control Register (PCR)
245
Format of the Receive Channel Enable Registers (RCERA-RCERH)
253
Document Revision History
274
Advertisement
Texas Instruments TMS320VC5501 Instruction Cache (30 pages)
Fixed-Point Digital Signal Processor Reference Guide
Brand:
Texas Instruments
| Category:
Signal Processors
| Size: 0.24 MB
Table of Contents
Table of Contents
7
Introduction
9
Conceptual Block Diagram of the I-Cache in the DSP System
10
2-Way Cache
11
I-Cache Operation
12
How the I-Cache Uses the Fetch Address
13
Instruction Presence Check and the Corresponding I-Cache Response
13
Fetch Address Fields for the 2-Way Cache
13
Fetch Address Field Descriptions for the 2-Way Cache
13
Line Load Process
14
Instruction Presence Check and I-Cache Response
14
Flow Chart of the Line Load Process
15
CPU Bits for Controlling the I-Cache
16
CAEN Bit to Enable or Disable the I-Cache
16
CACLR Bit to Flush the I-Cache
16
CAFRZ Bit to Freeze the Contents of the I-Cache
17
Configuring and Enabling the I-Cache
18
Timing Considerations
19
Hit Time
19
Miss Penalty
20
Power, Emulation, and Reset Considerations
21
Emulator Access
21
Effect of Setting a Software Breakpoint
21
Reconfiguration Required after a DSP Reset
21
Cache Registers
22
Global Control Register (ICGC)
22
I-Cache Global Control Register (ICGC)
22
Summary of the I-Cache Registers
22
I-Cache Global Control Register (ICGC) Bits
23
Flush Line Address Registers (ICFARL and ICFARH)
24
I-Cache Flush Line Low Address Register (ICFARL)
24
I-Cache Flush Line High Address Register (ICFARH)
24
I-Cache Flush Line Low Address Register (ICFARL) Bits
24
I-Cache Flush Line High Address Register (ICFARH) Bits
24
Way Miss Counter Register (ICWMC)
25
I-Cache Way Miss-Counter Register (ICWMC)
25
I-Cache Way Miss Counter Register (ICWMC) Bits
25
Revision History
27
Index
29
Advertisement
Related Products
Texas Instruments TMS320VC5402
Texas Instruments TMS320VC5502
Texas Instruments TMS320VC5503
Texas Instruments TMS320VC5507
Texas Instruments TMS320VC5510
Texas Instruments TMS320VC5509A
Texas Instruments TMS320F2806 Data
Texas Instruments TMS320C54x
Texas Instruments TMS320F2811
Texas Instruments TMS320C2810
Texas Instruments Categories
Motherboard
Control Unit
Microcontrollers
Computer Hardware
Calculator
More Texas Instruments Manuals
Login
Sign In
OR
Sign in with Facebook
Sign in with Google
Upload manual
Upload from disk
Upload from URL