Video Port Interrupt Enable Register (Vpie); Video Port Interrupt Enable Register (Vpie) Field Descriptions - Texas Instruments TMS320C64x DSP Reference Manual

2.7.3

Video Port Interrupt Enable Register (VPIE)

The video port interrupt enable register (VPIE) enables sources of the video
port interrupt to the DSP. The VPIE is shown in Figure 2–5 and described in
Table 2–8.
Figure 2–5. Video Port Interrupt Enable Register (VPIE)
31
23 22
LFDB SFDB
R/W-0 R/W-0
15 14
Reserved DCNA
R-0 R/W-0
7 6
LFDA SFDA
R/W-0 R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 2–8. Video Port Interrupt Enable Register (VPIE) Field Descriptions
†
Bit field symval
31–24 Reserved –
23 LFDB
DISABLE
ENABLE
22 SFDB
DISABLE
ENABLE
21 VINTB2
DISABLE
ENABLE
† For CSL implementation, use the notation VP_VPIE_field_symval
SPRU629
Reserved
R-0
21 20
VINTB2 VINTB1 SERRB
R/W-0 R/W-0
13 12
DCMP DUND
R/W-0 R/W-0
5 4
VINTA2 VINTA1 SERRA
R/W-0 R/W-0
†
Value Description
0 Reserved. The reserved bit location is always read as 0. A value
written to this field has no effect.
Long field detected on channel B interrupt enable bit.
0 Interrupt is disabled.
1 Interrupt is enabled.
Short field detected on channel B interrupt enable bit.
0 Interrupt is disabled.
1 Interrupt is enabled.
Channel B field 2 vertical interrupt enable bit.
0 Interrupt is disabled.
1 Interrupt is enabled.
Video Port Control Registers
19 18
CCMPB COVRB
R/W-0 R/W-0 R/W-0
11 10 9
TICK STC
R/W-0 R/W-0
3 2
CCMPA COVRA
R/W-0 R/W-0 R/W-0
Video Port
24
17 16
GPIO
R/W-0
8
Reserved
R-0
1 0
VIE
R/W-0
2-21