Video Capture Fifo Configurations; Bt.656 Video Capture Fifo Configuration - Texas Instruments TMS320C64x DSP Reference Manual

Dsp video port/vcxo interpolated control (vic) port
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Video Port FIFO
1.2.2

Video Capture FIFO Configurations

During video capture operation, the video port FIFO has one of four configura-
tions depending on the capture mode. For BT.656 operation, the FIFO is split
into channel A and B, as shown in Figure 1–2. Each FIFO is clocked indepen-
dently with the channel A FIFO receiving data from the VDIN[9–0] half of the
bus and the channel B FIFO receiving data from the VDIN[19–10] half of the
bus. Each channel's FIFO is further split into Y, Cb, and Cr buffers with sepa-
rate write pointers and read registers (YSRCx, CBSRCx, and CRSRCx).
Figure 1–2. BT.656 Video Capture FIFO Configuration
VDIN[9–0]
VDIN[19–10]
1-6
Overview
Capture FIFO A
8/10
Y Buffer A (1280 bytes)
Cb Buffer A (640 bytes)
8/10
Cr Buffer A (640 bytes)
8/10
Capture FIFO B
8/10
Y Buffer B (1280 bytes)
Cb Buffer B (640 bytes)
8/10
Cr Buffer B (640 bytes)
8/10
YSRCA
64
CBSRCA
64
CRSRCA
64
YSRCB
64
CBSRCB
64
CRSRCB
64
SPRU629

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