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Texas Instruments TMS320C6000 Manual

Texas Instruments TMS320C6000 Manual

Host port to mc68360 interface
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Download this manual See also: Reference Manual, User Manual
Zoran Nikolic
This application report describes an interface between the Motorola MC68360 quad
integrated communication controller (QUICC) and the host port interface (HPI) of a
TMS320C6000 (C6000) digital signal processor (DSP) device. This includes a schematic
showing connections between the two devices and verification that timing requirements are
met for each device (tables and timing diagrams).
NOTE: This application report has not been verified in a board design.
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Trademarks are the property of their respective owners.
TMS320C6000 and C6000 are trademarks of Texas Instruments.
TMS320C6000 Host Port to MC68360 Interface
ABSTRACT
Contents
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List of Figures
List of Tables
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Digital Signal Processing Solutions
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Application Report
SPRA545A - September 2001
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Summary of Contents for Texas Instruments TMS320C6000

  • Page 1: Table Of Contents

    This application report describes an interface between the Motorola MC68360 quad integrated communication controller (QUICC) and the host port interface (HPI) of a TMS320C6000 (C6000) digital signal processor (DSP) device. This includes a schematic showing connections between the two devices and verification that timing requirements are met for each device (tables and timing diagrams).

  • Page 2: Mc68360 Processor Interface

    HBE0 HBE1 HDS1 CONFIG2 HDS2 CONFIG1 CONFIG0 AVEC IRQx HINT *TMS320C6201/C6701 Only Figure 1. MC68360 to TMS320C62x/C67x/C64x (HPI16) HPI Interface Block Diagram TMS320C62x, TMS320C67x, TMS320C64x, C62x, C67x and C64x are trademarks of Texas Instruments. TMS320C6000 Host Port to MC68360 Interface...

  • Page 3: Figure 2 Mc68360 To Tms320C64X (Hpi32) Hpi Interface Block Diagram

    TMS320C6211 does not have HBE[1:0] signals. HBE1 See above. CONFIG[2:0] Because CONFIG[2:1] is set to 10, the CPU is enabled and the MBAR register is at 0x003FF00. 16-bit interface 32-bit interface CONFIG[2:0]=’101’ CONFIG[2:0]=’100’ TMS320C6000 Host Port to MC68360 Interface...

  • Page 4: Configuration

    (DSACK1) until after DS is asserted. Because of this timing conflict, HDS1 and HDS2 of the TMS320C6000 HPI are tied logic low and high, respectively, to enable data strobe at all times. The HPI must keep DSACKx asserted until it detects the negation of AS or DS (whichever it detects first).

  • Page 5: Table 2. Base Register 0 (Br0) Relevant Bits (Mc68360)

    DRAM/SRAM region is being accessed by an internal QUICC master. The option register is 32-bit read-write register that may be accessed at any time. TMS320C6000 Host Port to MC68360 Interface...

  • Page 6: Mc68360 To Hpi Timing Verification

    In all figures and tables, timing parameters are named in the same way as those in the data sheets for the TMS320C6000 and MC68360 devices. Actual timing parameter values are listed in Appendix A and Appendix B.

  • Page 7: Figure 3 Mc68360 Reads Internal Memory Of Tms320C62X/C67X/C64X (Hpi16 Mode)

    HCS/CS td(HCS–HRDY) td(HDV–HRDYL) tPLD HRDY tPLD tPLD tPLD DSACK1 td(HSTBH–HDHZ) td(HSTBL–HDV) th(HSTBL–HDLZ) th(HSTBH–HDV) th(HSTBH–HDV) HD[15:0]/ D[31:16] Figure 3. MC68360 Reads Internal Memory of TMS320C62x/C67x/C64x (HPI16 Mode) Using HPI (Read Without Auto-Increment) TMS320C6000 Host Port to MC68360 Interface...

  • Page 8: Figure 4 Mc68360 Write To Tms320C62X/C67X/C64X (Hpi16 Mode) Hpi

    HCS/CS tPLD tPLD tPLD tPLD DTACK1 th(HRDY–HSTBL) td(HCS–HRDY) tRADC tDOHC HRDY tCHDO tCHDH tSNDOI tRADC tSNDOI tCHDO tDOHC tCHDH HD[15:0]/ D[31:16] Figure 4. MC68360 Write to TMS320C62x/C67x/C64x (HPI16 Mode) HPI TMS320C6000 Host Port to MC68360 Interface...

  • Page 9: Figure 5 Mc68360 Reads Internal Memory Of Tms320C64X (Hpi32 Mode)

    HCS/CS td(HCS–HRDY) td(HDV–HRDYL) tPLD HRDY tPLD DSACK1 th(HSTBH–HDV) th(HSTBL–HDLZ) td(HSTBH–HDHZ) HD[31:0]/ D[31:0] Figure 5. MC68360 Reads Internal Memory of TMS320C64x (HPI32 Mode) Using HPI (Read Without Auto-Increment) TMS320C6000 Host Port to MC68360 Interface...

  • Page 10: Figure 6 Mc68360 Write To Tms320C64X (Hpi32 Mode) Hpi

    HHWIL/A[1] tAVSA tCLSN tCLSA tSNRN tSWA tw(HSTBL) th(HSTBH–HDV) HR/W/RW tsu(HDV–HSTBH) tSNAI HCS/CS tPLD tPLD DTACK1 td(HCS–HRDY) tDOHC tCHDO tCHDH HRDY tSNDOI HD[31:0]/ D[31:0] Figure 6. MC68360 Write to TMS320C64x (HPI32 Mode) HPI TMS320C6000 Host Port to MC68360 Interface...

  • Page 11: Table 4. Timing Requirements For The C6201/C6701 Hpi

    Hold time, HSTROBE low after HRDY low h(HRDYL-HSTBL) CLSN NOTE: P H = Period of TMS3206211/6711 DSP clock = 6 ns @ 167 MHz. P M = Period of MC68360 clock = 40 ns @ 25 MHz. TMS320C6000 Host Port to MC68360 Interface...

  • Page 12: References

    2. TMS320C6201 Digital Signal Processor (SPRS051). 3. TMS320C6701 Floating-Point Digital Signal Processor (SPRS067). 4. TMS320C6211, TMS320C6211B Fixed-Point Digital Signal Processors (SPRS073). 5. TMS320C6416 Fixed-Point Digital Signal Processor (SPRS164). 6. MC68360 Quad Integrated Communications Controller User’s Manual, Motorola, Inc. TMS320C6000 Host Port to MC68360 Interface...

  • Page 13: Appendix A Tms320C6X Timing Requirements

    || This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal. TMS320C6000 Host Port to MC68360 Interface...
  • Page 14 || This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal. TMS320C6000 Host Port to MC68360 Interface...
  • Page 15 NOTE: The timing specifications above are preliminary and the actual numbers may vary with a TMS part. Please refer to the latest data sheet for numbers. The timing requirements in the tables above are provided for quick reference only. For detailed description, notes, and restrictions, please see the data sheets listed in the section. TMS320C6000 Host Port to MC68360 Interface...

  • Page 16: Appendix B Mc68360 Timing Requirements

    DSACK asserted to DSACK valid (skew) [31A] DADV R/W width asserted (write or read) [46] Async input setup time [47A] AIST Async input hold time [47B] AIHT Data out from CLKO1 high [53] DOHC TMS320C6000 Host Port to MC68360 Interfacee...
  • Page 17 SPRA545A Table B–1. Motorola MC68360 Timing Parameters (Continued) Symbol Characteristic (ns) (ns) CLKO1 high to data-out high Z [54] CHDH R/W asserted to data bus impedance change [55] RADC The timing requirements in are provided for quick reference only. For detailed description, notes, and restrictions, please see the MC68360 Quad Integrated Communications Controller User’s Manual.
  • Page 18 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

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