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/* ––––––––––––––––––––––––––––––––––––––––––––––––– */
/* Define vertical blanking bit(VD_VBITn) reg values */
/* ––––––––––––––––––––––––––––––––––––––––––––––––– */
#define VD_VBIT_SET1
#define VD_VBIT_CLR1
#define VD_VBLNK1_SIZE
#define VD_VBIT_SET2
#define VD_VBIT_CLR2
#define VD_VBLNK2_SIZE
/* –––––––––––– */
/* Field timing */
/* –––––––––––– */
#define VD_FIELD1_XSTART
#define VD_FIELD1_YSTART
#define VD_FIELD1_XSTART
#define VD_FIELD1_YSTART
/* –––––––––––––––––––––––––––––––––––– */
/* Define field bit(VD_FBIT) reg values */
/* –––––––––––––––––––––––––––––––––––– */
#define VD_FBIT_CLR
#define VD_FBIT_SET
/* –––––––––––––––––––––––––––––––– */
/* Define horzontal synchronization */
/* –––––––––––––––––––––––––––––––– */
#define VD_HSYNC_START
#define VD_HSYNC_STOP
/* –––––––––––––––––––––––––––––––––––––––––– */
/* Define vertical synchronization for field1 */
/* –––––––––––––––––––––––––––––––––––––––––– */
#define VD_VSYNC_XSTART1
#define VD_VSYNC_YSTART1
#define VD_VSYNC_XSTOP1
#define VD_VSYNC_YSTOP1
SPRU629
Example 2: Noncontinuous Frame Display for 525/60 Format
1
/* first line with an EAV with V=1
/* indicating the start of Field1
/* vertical blanking
20
/* first line with an EAV with V=0
/* indicating the start of Field1
/* active display
(VD_VBIT_CLR1 – VD_VBIT_SET1) /* 19 lines
264 /* first line with an EAV with V=1
/* indicating the start of Field2
/* vertical blanking
283 /* first line with an EAV with V=0
/* indicating the start of Field2
/* active display
(VD_VBIT_CLR2 – VD_VBIT_SET2) /* 19 lines
720 /* pixel on the first line of
/* Field1 on which FLD ouput
/* is de–asserted
1
/* line on which FLD is de–asserted
360 /* pixel on the first line of
/* Field1 on which FLD ouput
/* is asserted
263 /* line on which FLD is asserted
4
/* first line with an EAV with F=0
/* indicating Field 1 display
266 /* first line with an EAV with F=1
/* indicating Field 2 display
736
800
720
4
720
7
Video Port Configuration Examples
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A-11
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