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Table 3–15. Video Capture Channel A Control Register (VCACTL)
Field Descriptions (Continued)
†
Bit
field
symval
18
FLDD
EAVFID
FDL
17
VRST
V1EAV
V0EAV
16
HRST
EAV
SAV
15
VCEN
DISABLE
ENABLE
14–13 PK10B
ZERO
SIGN
DENSEPK
–
† For CSL implementation, use the notation VP_VCACTL_field_symval
‡ For complete encoding of these bits, see Table 3–6, Table 3–11, and Table 3–12.
SPRU629
†
Value
BT.656 or Y/C Mode
Field detect method bit. (Channel A only)
st
0
1
line EAV or FID
input.
1
Field detect logic.
VCOUNT reset method bit.
0
Start of vertical blank
st
(1
V = 1 EAV or
VCTL2 active edge)
1
End of vertical blank
st
(1
V = 0 EAV or
VCTL2 inactive edge)
HCOUNT reset method bit.
0
EAV or
VCTL1 active edge.
1
SAV or
VCTL1 inactive edge.
Video capture enable bit. Other bits in VCACTL (except RSTCH
and BLKCAP bits) may only be changed when VCEN = 0.
0
Video capture is disabled.
1
Video capture is enabled.
10-bit packing format select bit.
0
Zero extend
1h
Sign extend
2h
Dense pack (zero
extend)
3h
Reserved
Video Capture Registers
Description
Raw Data Mode
TSI Mode
Not used.
Not used.
Not used.
Not used.
Not used.
Not used.
Not used.
Not used.
Not used.
Not used.
Not used.
Not used.
Zero extend
Not used.
Sign extend
Not used.
Dense pack (zero
Not used.
extend)
Reserved
Not used.
Video Capture Port
3-55
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