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If software sets the PEREN bit in PCR but the VPHLT bit in VPCTL remains
set:
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2.1.3
Software Port Reset
A software port reset may be performed on the entire video port by setting the
VPRST bit in VPCTL. This behaves identically to the peripheral bus reset
except that it does not clear the PEREN bit in PCR. This reset:
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Once the port is configured and the VPHLT bit is cleared, the setting of other
VPCTL bits (except VPRST) is disabled. The VCLK2 output may also be driven
at this time, if display mode is selected. VCTL1–3 must remain in a high-imped-
ance state unless enabled as GPIO, since internal/external sync is selected
through VDCTL.
2.1.4
Capture Channel Reset
A software reset may be performed on a single capture channel by setting the
RSTCH bit in VCxCTL. This reset requires that the channel VCLKIN be trans-
itioning. On capture channel reset:
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SPRU629
VCLK1, VCLK2, and STCLK are enabled to the port (allowing logic reset
to complete).
Peripheral bus accesses are acknowledged (RREADY/WREADY
returned) to prevent DMA lock-up. (Any value returned on reads, data
accepted or discarded on writes.)
Peripheral bus MMR interface allows access to all registers.
Port I/Os (VD[19–0], VCTL1, VCTL2, VCTL3, and VCLK2) remain in a
high-impedance state unless enabled as GPIO by the PFUNC bits.
VPCTL bits may be set (until the VPHLT bit is cleared).
Performs an asynchronous reset on all port logic (channel logic may stay
in reset until port input clock pulses occur).
Self-clears the VPRST bit to 0 but leaves the VPHLT bit set.
No new DMA events are generated.
Peripheral bus accesses are acknowledged (RREADY returned) to prevent
DMA lock-up. (Any value returned on reads)
Channel capture registers are set to their default values.
Channel capture FIFO is flushed (pointers reset).
The VCEN bit in VCxCTL is cleared to 0.
The RSTCH bit self-clears to 0 after completion of the above.
Reset Operation
Video Port
2-3
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