Video Display Fifo Configurations; Bit Raw Video Capture Fifo Configuration; Bt.656 Video Display Fifo Configuration - Texas Instruments TMS320C64x DSP Reference Manual

For 16/20-bit raw video, the FIFO is configured as a single buffer, as shown
in Figure 1–5. The FIFO receives 16/20-bit data from the VDIN[19–0] bus. The
FIFO has a single write pointer and read register (YSRCA).
Figure 1–5. 16/20-Bit Raw Video Capture FIFO Configuration
VDIN[19–0]
1.2.3

Video Display FIFO Configurations

During video display operation, the video port FIFO has one of five configura-
tions depending on the display mode. For BT.656 operation, a single output
is provided on channel A, as shown in Figure 1–6, with data output on
VDOUT[9–0]. The channel's FIFO is split into Y, Cb, and Cr buffers with
separate read pointers and write registers (YDSTA, CBDST, and CRDST).
Figure 1–6. BT.656 Video Display FIFO Configuration
YDSTA
CBDST
CRDST
SPRU629
Capture FIFO
16/20
Data Buffer
(5120 bytes)
Display FIFO
64
Y Buffer
(2560 bytes)
Cb Buffer
64
(1280 bytes)
Cr Buffer
64
(1280 bytes)
Video Port FIFO
YSRCA
64
8/10
VDOUT[9–0]
8/10
8/10
Overview 1-9