Texas Instruments TMS320C64x DSP Reference Manual page 61

Dsp video port/vcxo interpolated control (vic) port
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Video Port Control Registers
Table 2–9. Video Port Interrupt Status Register (VPIS) Field Descriptions (Continued)
Bit
field
symval
7
LFDA
NONE
CLEAR
6
SFDA
NONE
CLEAR
5
VINTA2
NONE
CLEAR
4
VINTA1
NONE
CLEAR
† For CSL implementation, use the notation VP_VPIS_field_symval
2-28
Video Port
Value
Description
Long field detected on channel A interrupt detected bit. (A long
field is only detected when the VRST bit in VCACTL is cleared to
0; when VRST = 1, a long field is always detected.)
BT.656 or Y/C capture mode – LFDA is set when long field
detection is enabled and VCOUNT is not reset before
VCOUNT = YSTOP + 1.
Raw data mode, or TSI capture mode or display mode – Not used.
0
No interrupt is detected.
1
Interrupt is detected. Bit is cleared.
Short field detected on channel A interrupt detected bit.
BT.656 or Y/C capture mode – SFDA is set when short field
detection is enabled and VCOUNT is reset before
VCOUNT = YSTOP.
Raw data mode, or TSI capture mode or display mode – Not used.
0
No interrupt is detected.
1
Interrupt is detected. Bit is cleared.
Channel A field 2 vertical interrupt detected bit.
BT.656, or Y/C capture mode or any display mode – VINTA2 is set
when a vertical interrupt occurred in field 2.
Raw data mode or TSI capture mode – Not used.
0
No interrupt is detected.
1
Interrupt is detected. Bit is cleared.
Channel A field 1 vertical interrupt detected bit.
BT.656, or Y/C capture mode or any display mode – VINTA1 is set
when a vertical interrupt occurred in field 1.
Raw data mode or TSI capture mode – Not used.
0
No interrupt is detected.
1
Interrupt is detected. Bit is cleared.
SPRU629

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