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Display Timing Examples
4.9.2
Interlaced Raw Display Example
This section shows an example of raw display output for the same 704
408
interlaced image.
The horizontal output timing is shown in Figure 4–35. This diagram assumes
that there is a two VCLK pipeline delay between the internal counter changing
and the output on external pins. The actual delay can be longer or shorter as
long as it is consistent within any display mode. The active line is 720-pixels
wide. Figure 4–35 shows the 704-pixel image window centered in the screen
that results in an IMGHOFFx of 8 pixels.
The HBLNK and HSYNC signals are shown as they would be output for active-
low operation. Note that only one of the two signals is actually available exter-
nally. The HBLNK inactive edge occurs on sample 0.
The IPCOUNT operation follows the description in section 4.1.2. IPCOUNT
resets to 0 at the first displayed pixel (FPCOUNT = IMGHOFFx) and stops
counting at the last displayed pixel (IPCOUNT = IMGHSIZEx). Both the
IPCOUNT and FPCOUNT counters increment on every third VCLKIN rising
VDTHRLD
edge, as programmed by the INCPIX bits in
with a value of 3.
VDOUT shows the output data and switching between Default Data, and FIFO
Data. Three values are output sequentially on VDOUT for each pixel count.
Note that the default value is output during both the blanking and nondisplay
image active video regions.
SPRU629
Video Display Port
4-39
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