Single-Rate Clock Example - Texas Instruments TMS320VC5501 Reference Manual

3.6.2 Single-Rate ST-Bus Clock
Figure 3−6. Single-Rate Clock Example
CLKS
FSR external
Internal FSG, FSR,
internal FSX
Internal CLKG, CLKR,
internal CLKX
(first FSR)
DR, DX (first FSR)
Internal CLKG, CLKR,
(subsequent FSR)
DR, DX
(subsequent FSR)
SPRU592E
FSRP/FSXP = 1: Active-low frame-sync pulse
-
RFRLEN1/XFRLEN1 = 11111b: 32 words per frame
-
RWDLEN1/XWDLEN1 = 0: 8 bits per word
-
RPHASE/XPHASE = 0: Single-phase frame and thus (R/X)FRLEN2 and
-
(R/X)WDLEN2 are ignored
RDATDLY/XDATDLY = 0: No data delay
-
The clock synchronization provided through the GSYNC bit is not supported
on TMS320VC5501 and TMS320VC5502 devices.
The example in Figure 3−6 is the same as the double-rate ST-bus clock
example in section 3.6.1 except that:
CLKGDV = 0: CLKS drives internal CLK(R/X) without any divide down
-
(single-rate clock).
CLKSP = 0: Rising edge of CLKS generates CLKG and internal CLK(R/X)
-
Á Á
W1B7 W1B6
Á Á
W32B0 W1B7 W1B6
The rising edge of CLKS is used to detect the external FSR pulse, which is
used to resynchronize internal McBSP clocks and generate a frame-sync
pulse for internal use. The internal frame-sync pulse is generated so that it is
wide enough to be detected on the falling edge of internal clocks.
The clock synchronization provided through the GSYNC bit is not supported
on TMS320VC5501 and TMS320VC5502 devices.
Sample Rate Generator Clocking Examples
W1B5 W1B4 W1B3 W1B2
W1B5 W1B4 W1B3 W1B2
Sample Rate Generator of the McBSP
W1B1 W1B0 W2B7
W1B1 W1B0 W2B7
WxBy = Word x Bit y
3-15