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Table 4–7. Video Display Control Register (VDCTL) Field Descriptions (Continued)
†
†
Bit
Bit
field
field
symval
symval
‡
6
FRAME
NONE
FRMDIS
‡
5
DF2
NONE
FLDDIS
‡
4
DF1
NONE
FLDDIS
3
Reserved –
2–0
DMODE
BT656B
BT656D
RAWB
RAWD
YC16
YC20
RAW16
RAW20
† For CSL implementation, use the notation VP_VDCTL_field_symval
‡ For complete encoding of these bits, see Table 4–4.
SPRU629
BT.656 and Y/C Mode
†
†
Value
Value
Display frame bit.
0
Do not display frame.
1
Display frame.
Display field 2 bit.
0
Do not display field 2.
1
Display field 2.
Display field 1 bit.
0
Do not display field 1.
1
Display field 1.
0
Reserved. The reserved bit location is always read as 0. A value
written to this field has no effect.
Display mode select bit.
0
Enables 8-bit BT.656 mode.
1h
Enables 10-bit BT.656 mode.
2h
Enables 8-bit raw data mode.
3h
Enables 10-bit raw data mode.
4h
Enables 8-bit Y/C mode.
5h
Enables 10-bit Y/C mode.
6h
Enables 16-bit raw data mode.
7h
Enables 20-bit raw data mode.
Video Display Registers
Description
Raw Data Mode
Video Display Port
4-59
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