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Displaying Video in BT.656 or Y/C Mode
12) Configure a DMA to move data from the Y buffer in the DSP memory to
13) Configure a DMA to move data from the Cb buffer in the DSP memory to
14) Configure a DMA to move data from the Cr buffer in the DSP memory to
15) Set DISPEVT1 and DISPEVT2 bits in VDDISPEVT. Event count is total
16) Write to VPIE to enable underrun (DUND) and display complete (DCMP)
17) Write to VDTHRLD to set the display FIFO threshold (VDTHRLD bits).
18) Write to VDCTL to:
19) Wait for 2 or more frame times, to allow the display counters and control
20) Write to VDCTL to clear the BLKDIS bit.
21) Display is enabled at the start of the first frame after BLKDIS = 0 and
4-48
Video Display Port
YDSTA (memory-mapped Y display FIFO). The transfers should be
triggered by the YEVT.
CBDST (memory-mapped Cb display FIFO). The transfers should be
triggered by the CbEVT. The size of the transfers should be set to ½ the
Y transfer size.
CRDST (memory-mapped Cr display FIFO). The transfers should be
triggered by the CrEVT. The size of the transfers should be set to ½ the
Y transfer size.
doublewords per field divided by total doublewords per Y DMA.
interrupts, if desired.
-
Set display mode (DMODE = 00x for BT.656 output, 10x for Y/C
output).
-
Set desired field/frame operation (CON, FRAME, DF1, DF2 bits).
-
Select control outputs (VCTL1S, VCTL2S, VCTL3S bits) or external
sync inputs (HXS, VXS, FXS bits).
-
Enable scaling (SCALE and RESMPL bits), if desired and in 8-bit
mode.
-
Select 10-bit unpacking mode (DPK bit), if appropriate.
-
Set VDEN bit to enable the display.
signals to become properly synchronized.
begins with the first selected field. DMA events are generated as triggered
by VDTHRLD and the DEVTCT counter. When a selected field has been
displayed (FLCOUNT = FRMHEIGHT and FPCOUNT = FRMWIDTH),
the appropriate F1D, F2D, or FRMD bits are set and cause the DCMP bit
in VPIS to be set. This generates a DSP interrupt, if the DCMP bit is
enabled in VPIE.
SPRU629
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