Field Descriptions - Texas Instruments TMS320C64x DSP Reference Manual

Video Capture Registers
Table 3–15. Video Capture Channel A Control Register (VCACTL)
Field Descriptions (Continued)
†
Bit field symval
12 LFDE
DISABLE
ENABLE
11 SFDE
DISABLE
ENABLE
10 RESMPL
DISABLE
ENABLE
9 Reserved –
8 SCALE
NONE
HALF
‡
7 CON
DISABLE
ENABLE
† For CSL implementation, use the notation VP_VCACTL_field_symval
‡ For complete encoding of these bits, see Table 3–6, Table 3–11, and Table 3–12.
3-56 Video Capture Port
†
Value BT.656 or Y/C Mode
Long field detect enable bit.
0 Long field detect
is disabled.
1 Long field detect
is enabled.
Short field detect enable bit.
0 Short field detect
is disabled.
1 Short field detect
is enabled.
Chroma resampling enable bit.
0 Chroma resampling is
disabled.
1 Chroma is horizontally
resampled from
4:2:2 co-sited to
4:2:0 interspersed
before saving to
chroma buffers.
0 Reserved. The reserved bit location is always read as 0. A value
written to this field has no effect.
Scaling select bit.
0 No scaling
½ scaling
1
Continuous capture enable bit.
0 Continuous capture is disabled.
1 Continuous capture is enabled.
Description
Raw Data Mode TSI Mode
Not used. Not used.
Not used. Not used.
Not used. Not used.
Not used. Not used.
Not used. Not used.
Not used. Not used.
Not used. Not used.
Not used. Not used.
SPRU629