Table of Contents
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Index
VDCLIP 4-85
VDCTL 4-55
VDDEFVAL 4-86
VDDISPEVT 4-84
VDEN 4-55
VDFBIT 4-89
VDFLD bit 4-53
VDFLDT1 4-74
VDFLDT2 4-75
VDFRMSZ 4-60
VDHBLNK 4-61
VDHSYNC 4-78
VDIMGOFF1 4-68
VDIMGOFF2 4-71
VDIMGSZ1 4-70
VDIMGSZ2 4-73
VDRELOAD 4-83
VDSTAT 4-53
VDTHRLD 4-76
VDTHRLD1 bits 4-76
VDTHRLD2 bits 4-76
VDVBIT1 4-90
VDVBIT2 4-92
VDVBLKE1 4-64
VDVBLKE2 4-67
VDVBLKS1 4-62
VDVBLKS2 4-65
VDVINT 4-88
VDVSYNE1 4-80
VDVSYNE2 4-82
VDVSYNS1 4-79
VDVSYNS2 4-81
VDXPOS bits 4-53
VDYPOS bits 4-53
VIC clock divider register (VICDIV) 6-9
VIC control register (VICCTL) 6-6
VIC input register (VICIN) 6-8
VIC port
enabling 6-5
features 6-2
interface 6-3
operational details 6-3
overview 6-2
registers 6-5
Index-8
VICCLKDIV bits 6-9
VICCTL 6-6
VICDIV 6-9
VICIN 6-8
VICINBITS bits 6-8
video capture
FIFO configurations 1-6
FIFO registers 3-83
mode selection 3-2
overview 3-1
registers 3-49
signal mapping 1-13
throughput 2-13
video capture channel A control register
(VCACTL) 3-53
video capture channel A event count register
(VCAEVTCT) 3-67
video capture channel A field 1 start register
(VCASTRT1) 3-58
video capture channel A field 1 stop register
(VCASTOP1) 3-60
video capture channel A field 2 start register
(VCASTRT2) 3-61
video capture channel A field 2 stop register
(VCASTOP2) 3-62
video capture channel A status register
(VCASTAT) 3-50
video capture channel A threshold register
(VCATHRLD) 3-65
video capture channel A vertical interrupt register
(VCAVINT) 3-63
video capture channel B control register
(VCBCTL) 3-68
video capture channel B event count register
(VCBEVTCT) 3-67
video capture channel B field 1 start register
(VCBSTRT1) 3-58
video capture channel B field 1 stop register
(VCBSTOP1) 3-60
video capture channel B field 2 start register
(VCBSTRT2) 3-61
video capture channel B field 2 stop register
(VCBSTOP2) 3-62
video capture channel B status register
(VCBSTAT) 3-50
video capture channel B threshold register
(VCBTHRLD) 3-65
SPRU629
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Table of Contents
