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GPIO Registers
5.1.3
Video Port Pin Function Register (PFUNC)
The video port pin function register (PFUNC) selects the video port pins as
GPIO. The PFUNC is shown in Figure 5–3 and described in Table 5–4. Each
bit controls either one pin or a set of pins. When a bit is set to 1, it enables the
pin(s) that map to it as GPIO. The GPIO feature should not be used for pins
that are used as part of the capture or display operation. For pins that have
been muxed out for use by another peripheral, the PFUNC bits will have no
effect.
The VDATA pins are broken into two functional groups: VDATA[9–0] and
VDATA[19–10]. Thus, each entire half of the data bus must be configured as
either functional pins or GPIO pins. In the case of single BT.656 or raw 8/10-bit
mode, the upper 10 VDATA pins (VDATA[19–10]) can be used as GPIOs. If the
video port is disabled, all pins can be used as GPIO.
Figure 5–3. Video Port Pin Function Register (PFUNC)
31
Reserved
R-0
15
11
Reserved
PFUNC10
R-0
R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 5–4. Video Port Pin Function Register (PFUNC) Field Descriptions
†
Bit
field
symval
31–23 Reserved
–
22
PFUNC22
NORMAL
VCTL3
21
PFUNC21
NORMAL
VCTL2
† For CSL implementation, use the notation VP_PFUNC_field_symval
5-6
General Purpose I/O Operation
23
22
PFUNC22
R/W-0
10
9
†
Value
Description
0
Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
PFUNC22 bit determines if VCTL3 pin functions as GPIO.
0
Pin functions normally.
1
Pin functions as GPIO pin.
PFUNC21 bit determines if VCTL2 pin functions as GPIO.
0
Pin functions normally.
1
Pin functions as GPIO pin.
21
20
19
PFUNC21
PFUNC20
R/W-0
R/W-0
Reserved
R-0
16
Reserved
R/W-0
1
0
PFUNC0
R/W-0
SPRU629
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