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Texas Instruments TMS320C645x DSP User Manual

Dsp ethernet media access controller (emac)/ management data input/output (mdio)
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TMS320C645x DSP
Ethernet Media Access Controller (EMAC)/
Management Data Input/Output (MDIO)
User's Guide
Literature Number: SPRU975B
August 2006

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Summary of Contents for Texas Instruments TMS320C645x DSP

  • Page 1 TMS320C645x DSP Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) User's Guide Literature Number: SPRU975B August 2006...
  • Page 2 SPRU975B – August 2006 Submit Documentation Feedback...

  • Page 3: Table Of Contents

    Preface Introduction Purpose of the Peripheral Features Functional Block Diagram Industry Standard(s) Compliance Statement EMAC Functional Architecture Clock Control Memory Map System Level Connections Ethernet Protocol Overview Programming Interface EMAC Control Module Management Data Input/Output (MDIO) Module EMAC Module Media Independent Interfaces 2.10 Packet Receive Operation 2.11...
  • Page 4 4.15 MDIO User PHY Select Register 1 (USERPHYSEL1) EMAC Port Registers Introduction Transmit Identification and Version Register (TXIDVER) Transmit Control Register (TXCONTROL) Transmit Teardown Register (TXTEARDOWN) Receive Identification and Version Register (RXIDVER) Receive Control Register (RXCONTROL) Receive Teardown Register (RXTEARDOWN) Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) 5.10...
  • Page 5 5.48 Transmit Channel 0-7 Completion Pointer Register (TXnCP) 5.49 Receive Channel 0-7 Completion Pointer Register (RXnCP) 5.50 Network Statistics Registers Appendix A Glossary Appendix B Revision History SPRU975B – August 2006 Submit Documentation Feedback Contents...
  • Page 6 EMAC and MDIO Block Diagram Ethernet Configuration with MII Interface Ethernet Configuration with RMII Interface Ethernet Configuration with GMII Interface Ethernet Configuration with RGMII Interface Ethernet Frame Basic Descriptor Format Typical Descriptor Linked List Transmit Descriptor Format Receive Descriptor Format EMAC Control Module Block Diagram MDIO Module Block Diagram EMAC Module Block Diagram...
  • Page 7 Receive Buffer Offset Register (RXBUFFEROFFSET) Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) MAC Control Register (MACCONTROL) MAC Status Register (MACSTATUS) Emulation Control Register (EMCONTROL) FIFO Control Register (FIFOCONTROL) MAC Configuration Register (MACCONFIG) Soft Reset Register (SOFTRESET)
  • Page 8 Interface Selection Pins EMAC and MDIO Signals for MII Interface EMAC and MDIO Signals for RMII Interface EMAC and MDIO Signals for GMII Interface EMAC and MDIO Signals for RGMII Interface Ethernet Frame Description Basic Descriptors Receive Frame Treatment Summary Middle of Frame Overrun Treatment Emulation Control EMAC Control Module Registers...
  • Page 9 Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions Receive Maximum Length Register (RXMAXLEN) Field Descriptions Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) Field Descriptions Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions MAC Control Register (MACCONTROL) Field Descriptions MAC Status Register (MACSTATUS) Field Descriptions...

  • Page 10: Preface

    (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache. TMS320C645x DSP Peripherals Overview Reference Guide (literature number SPRUE52) provides a brief description of the peripherals available on the TMS320C645x digital signal processors (DSPs).

  • Page 11: Introduction

    Ethernet Media Access Controller (EMAC)/Management Introduction This document provides a functional description of the Ethernet Media Access Controller (EMAC) and Physical layer (PHY) device Management Data Input/Output (MDIO) module integrated with TMS320C645x (C645x) devices. Included are the features of the EMAC and MDIO modules, a discussion of their architecture and operation, how these modules connect to the outside world, and the registers description for each module.

  • Page 12: Functional Block Diagram

    Introduction Functional Block Diagram Figure 1 shows the three main functional modules of the EMAC/MDIO peripheral: EMAC control module EMAC module MDIO module The EMAC control module is the main interface between the device core processor and the EMAC module and MDIO module. The EMAC control module contains the necessary components to allow the EMAC to make efficient use of device memory, plus it controls device interrupts.

  • Page 13: Industry Standard(S) Compliance Statement

    www.ti.com Industry Standard(s) Compliance Statement The EMAC peripheral conforms to the IEEE 802.3 standard, describing the “Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer” specifications. ISO / IEC has also adopted the IEEE 802.3 standard and re-designated it as ISO/IEC 8802-3:2000(E). In difference from this standard, the EMAC peripheral integrated with the C645x devices does not use the transmit coding error signal MTXER.

  • Page 14: Emac Functional Architecture

    EMAC Functional Architecture EMAC Functional Architecture This chapter discusses the architecture and basic function of the EMAC peripheral. Clock Control The frequencies for the transmit and receive clocks are fixed by the IEEE 802.3 specification as shown below: 2.5 Mhz at 10 Mbps 25 Mhz at 100 Mbps 125 MHz at 1000 Mbps The C645x device uses two PLL controllers to generate all of the clocks that the DSP needs.

  • Page 15: Memory Map

    www.ti.com For timing purposes, data in 10/100 mode is transmitted and received with reference to MTCLK and MRCLK, respectively. For 1000 Mbps mode, receive timing is the same, but transmit is relative to GMTCLK. 2.1.4 RGMII Clocking When the RGMII interface is selected by setting MACSEL to 11b, you must configure the internal clock (SYSCLK1) to a 125 MHz frequency by setting the divider for the secondary PLL controller to /5.

  • Page 16: System Level Connections

    EMAC Functional Architecture System Level Connections The C645x device supports four different interfaces to a physical layer device. You can only transfer data on one interface at a given time. Each of these interfaces is selected in hardware via the configuration pins (MACSEL[1:0]).

  • Page 17: Emac And Mdio Signals For Mii Interface

    www.ti.com Table 2 summarizes the individual EMAC and MDIO signals for the MII interface. For more information, refer to either the IEEE 802.3 standard or ISO/IEC 8802-3:2000(E). The EMAC module does not include a transmit error (MTXER) pin. If a transmit error occurs, CRC inversion is used to negate the validity of the transmitted frame.

  • Page 18: Ethernet Configuration With Rmii Interface

    EMAC Functional Architecture 2.3.2 Reduced Media Independent Interface (RMII) Connections Figure 3 shows a device with integrated EMAC and MDIO interfaced via a RMII connection. This interface is only available in 10 Mbps and 100 Mbps modes. The RMII interface is only supported in full-duplex mode for the C645x family of devices.

  • Page 19: Emac And Mdio Signals For Rmii Interface

    www.ti.com The RMII interface has the same functionality as the MII, but it does so with a reduced number of pins, thus lowering the total cost for an application. In devices incorporating many PHY interfaces such as switches, the number of pins can add significant cost as the port counts increase. individual EMAC and MDIO signals for the RMII interface.

  • Page 20: Ethernet Configuration With Gmii Interface

    EMAC Functional Architecture 2.3.3 Gigabit Media Independent Interface (GMII) Connections Figure 4 shows a device with integrated EMAC and MDIO interfaced via a GMII connection. This interface is available in 10 Mbps, 100 Mbps, and 1000 Mbps modes. Figure 4. Ethernet Configuration with GMII Interface System core The GMII interface supports 10/100/1000 Mbps modes.

  • Page 21: Emac And Mdio Signals For Gmii Interface

    www.ti.com Table 4 summarizes the individual EMAC and MDIO signals for the GMII interface. Table 4. EMAC and MDIO Signals for GMII Interface Signal Name MTCLK GMTCLK MTXD[7-0] MTXEN MCOL MCRS MRCLK MRXD[7-0] MRXDV MRXER MDCLK MDIO SPRU975B – August 2006 Submit Documentation Feedback Description Transmit clock (MTCLK).

  • Page 22: Ethernet Configuration With Rgmii Interface

    EMAC Functional Architecture 2.3.4 Reduced Gigabit Media Independent Interface (RGMII) Connections Figure 5 shows a device with integrated EMAC and MDIO interfaced via a RGMII connection. This interface is available in 10 Mbps, 100 Mbps, and 1000 Mbps modes. Figure 5. Ethernet Configuration with RGMII Interface System core The RGMII interface is a reduced pin alternative to the GMII interface.

  • Page 23: Emac And Mdio Signals For Rgmii Interface

    www.ti.com Table 5 summarizes the individual EMAC and MDIO signals for the RGMII interface. Table 5. EMAC and MDIO Signals for RGMII Interface Signal Name TXD[3-0] TXCTL REFCLK RXD[3-0] RXCTL MDCLK MDIO SPRU975B – August 2006 Submit Documentation Feedback Description Transmit clock (TXC).

  • Page 24: Ethernet Protocol Overview

    EMAC Functional Architecture Ethernet Protocol Overview Ethernet provides an unreliable, connectionless service to a networking application. A brief overview of the ethernet protocol follows. For more information on the carrier sense multiple access with collision detection (CSMA/CD) access method (ethernet’s multiple access protocol), see the IEEE 802.3 standard document.
  • Page 25 www.ti.com 2.4.2 Multiple Access Protocol Nodes in an ethernet local area network are interconnected by a broadcast channel. As a result, when an EMAC port transmits a frame, all of the adapters on the local network receive the frame. Carrier sense multiple access with collision detection (CSMA/CD) algorithms are used when the EMAC operates in half-duplex mode.

  • Page 26: Programming Interface

    EMAC Functional Architecture Programming Interface 2.5.1 Packet Buffer Descriptors The buffer descriptor is a central part of the EMAC module. It determines how the application software describes ethernet packets to be sent and empty buffers to be filled with incoming packet data. The basic descriptor format is shown in Word Offset Buffer Offset...

  • Page 27: Typical Descriptor Linked List

    www.ti.com For example, consider three packets to be transmitted, Packet A is a single fragment (60 bytes), Packet B is fragmented over three buffers (1514 bytes total), and Packet C is a single fragment (1514 bytes). Figure 8 shows the linked list of descriptors to describe these three packets. SPRU975B –...
  • Page 28 EMAC Functional Architecture 2.5.2 Transmit and Receive Descriptor Queues The EMAC module processes descriptors in linked list chains EMAC are maintained by the application software via the head descriptor pointer (HDP) registers. Since the EMAC supports eight channels for both transmit and receive, there are eight head descriptor pointer registers for both.
  • Page 29 www.ti.com 2.5.3 Transmit and Receive EMAC Interrupts The EMAC processes descriptors in linked list chains mechanism (Section 2.5.2). The EMAC synchronizes the descriptor list processing by using interrupts to the software application. The interrupts are controlled by the application by using the interrupt masks, global interrupt enable, and the completion pointer register (CP).

  • Page 30: Transmit Descriptor Format

    EMAC Functional Architecture 2.5.4 Transmit Buffer Descriptor Format A transmit (TX) buffer descriptor 32-bit boundary that describes a packet or a packet fragment. Example 1 shows the transmit buffer descriptor described by a C structure. (a) Word 0 (b) Word 1 (c) Word 2 Buffer Offset (d) Word 3...
  • Page 31 www.ti.com 2.5.4.1 Next Descriptor Pointer The next descriptor pointer indicates the 32-bit word aligned memory address of the next buffer descriptor in the transmit queue. The pointer creates a linked list of buffer descriptors. If the value of this pointer is zero, then the current buffer is the last buffer in the queue.
  • Page 32 EMAC Functional Architecture 2.5.4.7 End of Packet (EOP) Flag When set, this flag indicates that the descriptor points to the last packet buffer for a given packet. For a single fragment packet, both the start of packet (SOP) and EOP flags are set. Otherwise, the descriptor pointing to the last packet buffer for the packet sets the EOP flag.

  • Page 33: Receive Descriptor Format

    www.ti.com 2.5.5 Receive Buffer Descriptor Format A receive (RX) buffer descriptor 32-bit boundary that describes a packet or a packet fragment. Example 2 shows the receive descriptor described by a C structure. (a) Word 0 (b) Word 1 (c) Word 2 Buffer Offset (d) Word 3 OWNER...
  • Page 34 EMAC Functional Architecture 2.5.5.1 Next Descriptor Pointer The next descriptor pointer indicates the 32-bit word aligned memory address of the next buffer descriptor in the receive queue. The pointer creates a linked list of buffer descriptors. If the value of the pointer is zero, then the current buffer is the last buffer in the queue.
  • Page 35 www.ti.com 2.5.5.6 Start of Packet (SOP) Flag When set, this flag indicates that the descriptor points to the starting packet buffer of a new packet. For a single fragment packet, both the SOP and end of packet (EOP) flags are set. Otherwise, the descriptor pointing to the last packet buffer for the packet has the EOP flag set.
  • Page 36 EMAC Functional Architecture 2.5.5.14 Fragment Flag The EMAC sets this flag in the SOP buffer descriptor if the received packet is only a packet fragment and was not discarded because the RXCEFEN bit was set in the RXMBPENABLE register. 2.5.5.15 Undersized Flag The EMAC sets this flag in the SOP buffer descriptor if the received packet is undersized and was not discarded because the RXCSFEN bit was set in the RXMBPENABLE register.

  • Page 37: Emac Control Module

    www.ti.com EMAC Control Module The EMAC control module (Figure and provides a local memory space to hold EMAC packet buffer descriptors. Local memory is used to avoid contention to device memory spaces. Other functions include the bus arbiter, and interrupt logic control.

  • Page 38: Management Data Input/Output (Mdio) Module

    EMAC Functional Architecture 2.6.3 Interrupt Control The EMAC control module combines the multiple interrupt conditions generated by the EMAC and MDIO modules into a single interrupt signal that is mapped to a CPU interrupt via the CPU interrupt controller. The control module uses two registers to control the interrupt signal to the CPU. First, the INTEN bit in the EWCTL register globally enables and disables the interrupt signal to the CPU.

  • Page 39: Mdio Module Block Diagram

    www.ti.com Peripheral clock USERINT EMAC control module LINKINT Configuration bus 2.7.1.1 MDIO Clock Generator The MDIO clock generator controls the MDIO clock based on a divide-down of the peripheral clock (CPUclk/6) in the EMAC control module. The MDIO clock is specified to run up to 2.5 MHz, although typical operation would be 1.0 MHz.
  • Page 40 EMAC Functional Architecture 2.7.2 MDIO Module Operational Overview The MDIO module implements the 802.3 serial management interface to simultaneously interrogate and control up to two Ethernet PHYs, using a shared two-wired bus. It separately performs auto-detection and records the current link status of up to 32 PHYs, polling all 32 MDIO addresses. Application software uses the MDIO module to configure the auto-negotiation parameters of the primary PHY attached to the EMAC, retrieve the negotiation results, and configure required parameters in the EMAC.
  • Page 41 www.ti.com 2.7.2.2 Writing Data to a PHY Register The MDIO module includes a user access register (USERACCESSn) to directly access a specified PHY device. To write a PHY register, perform the following: 1. Ensure that the GO bit in the USERACCESSn register is cleared. 2.
  • Page 42 EMAC Functional Architecture The implementation of these macros using the register layer Chip Support Library (CSL) is shown in Example 3 (USERACCESS0 is assumed). Note that this implementation does not check the ACK bit on PHY register reads; in other words, it does not follow the procedure outlined in assumed that the PHY is acknowledging read operations.

  • Page 43: Emac Module

    www.ti.com EMAC Module Section 2.8 discusses the architecture and basic functions of the EMAC module. 2.8.1 EMAC Module Components The EMAC module (Figure 13) interfaces to PHY components through one of the four Media Independent Interfaces(MII, RMII, GMII, or RGMII), and interfaces to the system core through the EMAC control module.
  • Page 44 EMAC Functional Architecture 2.8.1.3 MAC Receiver The MAC receiver detects and processes incoming network frames, de-frames them, and places them into the receive FIFO. The MAC receiver also detects errors and passes statistics to the statistics RAM. 2.8.1.4 Receive Address This sub-module performs address matching and address filtering based on the incoming packet’s destination address.
  • Page 45 www.ti.com 2.8.1.12 Clock and Reset Logic The clock and reset sub-module generates all the clocks and resets for the EMAC peripheral. 2.8.2 EMAC Module Operational Overview After reset, initialization, and configuration of the EMAC, the application software running on the host may initiate transmit operations.

  • Page 46: Media Independent Interfaces

    EMAC Functional Architecture Media Independent Interfaces The EMAC supports four physical interfaces to external devices: Media Independent Interface (MII), Reduced Media Independent Interface (RMII), Gigabit Media Independent Interface (GMII), and Reduced Gigabit Media Independent Interface (RGMII). The physical interface used depends on the MACSEL pins. The basic operation of all four interfaces is the same, with some minor differences.
  • Page 47 www.ti.com 2.9.1.4 Collision-Based Receive Buffer Flow Control Collision-based receive buffer flow control provides a means of preventing frame reception when the EMAC is operating in half-duplex mode (FULLDUPLEX bit is cleared in MACCONTROL register). When receive flow control is enabled and triggered, the EMAC generates collisions for received frames. The jam sequence transmitted is the twelve byte sequence C3.C3.C3.C3.C3.C3.C3.C3.C3.C3.C3.C3 in hexadecimal.
  • Page 48 EMAC Functional Architecture 2.9.2 Data Transmission The EMAC passes data to the PHY from the transmit FIFO (when enabled). Data is synchronized to the transmit clock rate. Transmission begins when there are TXCELLTHRESH cells of 64 bytes each, or a complete packet, in the FIFO.
  • Page 49 www.ti.com 2.9.2.6 Transmit Flow Control When enabled, incoming pause frames are acted upon to prevent the EMAC from transmitting any further frames. Incoming pause frames are only acted upon when the FULLDUPLEX and TXFLOWEN bits in the MACCONTROL register are set. Pause frames are not acted upon in half-duplex mode. Pause frame action is taken if enabled, but normally the frame is filtered and not transferred to memory.

  • Page 50: 2.10 Packet Receive Operation

    EMAC Functional Architecture 2.10 Packet Receive Operation 2.10.1 Receive DMA Host Configuration To configure the receive DMA for operation, the host must perform the following actions: Initialize the receive addresses Initialize the RXnHDP registers to zero Write the MACHASH1 and MACHASH2 registers, if hash matching multicast addressing is desired Initialize the RXnFREEBUFFER, RXnFLOWTHRESH, and RXFILTERLOWTHRESH registers, if flow control is to be enabled Enable the desired receive interrupts using the RXINTMASKSET and RXINTMASKCLEAR registers...
  • Page 51 www.ti.com 2.10.3 Receive Channel Addressing The receive address block can store up to 32 addresses to be filtered or matched. Before enabling packet reception, all the address RAM locations should be initialized, including locations to be unused. The system software is responsible for adding and removing addresses from the RAM. A MAC address location in RAM is 53 bits wide and consists of: 48 bits of the MAC address 3 bits for the channel to which a valid address match will be transferred.
  • Page 52 EMAC Functional Architecture 2.10.5 Host Free Buffer Tracking The host must track free buffers for each enabled channel (including unicast, multicast, broadcast, and promiscuous) if receive QOS or receive flow control is used. Disabled channel free buffer values are don’t cares.

  • Page 53: Receive Frame Treatment Summary

    www.ti.com 2.10.8 Promiscuous Receive Mode When the promiscuous receive mode is enabled by setting the RXCAFEN bit in the RXMBPENABLE register, non-address matching frames that would normally be filtered are transferred to the promiscuous channel. Address matching frames that would normally be filtered due to errors are transferred to the address match channel when RXCAFEN and RXCEFEN bits are set.

  • Page 54: Middle Of Frame Overrun Treatment

    EMAC Functional Architecture Table 8. Receive Frame Treatment Summary (continued) ADDRESS MATCH RXCAFEN 2.10.9 Receive Overrun The types of receive overrun are: FIFO start of frame overrun (FIFO_SOF) FIFO middle of frame overrun (FIFO_MOF) DMA start of frame overrun (DMA_SOF) DMA middle of frame overrun (DMA_MOF) The statistics counters used to track these types of receive overrun are: Receive Start of Frame Overruns Register (RXSOFOVERRUNS)

  • Page 55: 2.11 Packet Transmit Operation

    www.ti.com 2.11 Packet Transmit Operation The transmit DMA is an eight channel interface. Priority between the eight queues may be either fixed or round robin as selected by the TXPTYPE bit in the MACCONTROL register. If the priority type is fixed, then channel 7 has the highest priority and channel 0 has the lowest priority.

  • Page 56: 2.13 Transfer Node Priority

    EMAC Functional Architecture Latency to system’s internal and external RAM can be controlled through the use of the transfer node priority allocation register in the C645x devices. Latency to descriptor RAM is low because RAM is local to the EMAC, as it is part of the EMAC control module. 2.13 Transfer Node Priority The C645x devices contain a system level priority allocation register (PRI_ALLOC) that sets the priority of the transfer node used in issuing memory transfer requests to system memory.

  • Page 57: 2.15 Initialization

    www.ti.com 2.15 Initialization 2.15.1 Enabling the EMAC/MDIO Peripheral When the device is powered on, the EMAC peripheral is disabled. Prior to EMAC-specific initialization, the EMAC must be enabled; otherwise its registers cannot be written, and the reads will all return a value of zero.
  • Page 58 EMAC Functional Architecture Example 4. EMAC Control Module Initialization Code Uint32 tmpval; // Globally disable EMAC/MDIO interrupts in the control module CSL_FINST(ECTL_REGS->EWCTL, ECTL_EWCTL_INTEN, DISABLE ); /* Wait about 100 cycles */ for( I=0; i<5; I++ ) tmpval = ECTL_REGS->EWCTL; /* Set Interrupt Timer Count (CPUclk/6) */ ECTL_REGS->EWINTTCNT = 1500 ;...
  • Page 59 www.ti.com 2.15.4 EMAC Module Initialization The EMAC module sends and receives data packets over the network by maintaining up to 8 transmit and receive descriptor queues. The EMAC module configuration must also be kept current based on the PHY negotiation results returned from the MDIO module. Programming this module is the most time-consuming aspect of developing an application or device driver for Ethernet.

  • Page 60: 2.16 Interrupt Support

    EMAC Functional Architecture 2.16 Interrupt Support 2.16.1 EMAC Module Interrupt Events and Requests The EMAC/MDIO generates 18 interrupt events, as follows: TXPENDn: Transmit packet completion interrupt for transmit channels 7 through 0 RXPENDn: Receive packet completion interrupt for receive channels 7 through 0 STATPEND: Statistics interrupt HOSTPEND: Host error interrupt 2.16.1.1...
  • Page 61 www.ti.com 2.16.1.2 Receive Packet Completion Interrupts The receive DMA engine has eight channels, and each channel has a corresponding interrupt (RXPENDn). The receive interrupts are level interrupts that remain asserted until cleared by the CPU. Each of the eight receive channel interrupts may be individually enabled by setting the appropriate bit in the RXINTMASKSET register.
  • Page 62 EMAC Functional Architecture 2.16.1.4 Host Error Interrupt The host error interrupt (HOSTPEND) is issued, if enabled, under error conditions due to the handling of buffer descriptors detected during transmit or receive DMA transactions. The failure of the software application to supply properly formatted buffer descriptors results in this error. The error bit can only be cleared by resetting the EMAC module in hardware.

  • Page 63: 2.17 Power Management

    www.ti.com 2.16.3 Proper Interrupt Processing All the interrupts signaled from the EMAC and MDIO modules are level-driven. If they remain active, their level remains constant. However, the CPU core requires edge-triggered interrupts. To properly convert the level-driven interrupt signal to an edge-triggered signal, the application software must use the interrupt control logic of the EMAC control module.

  • Page 64: Emac Control Module Registers

    EMAC Control Module Registers EMAC Control Module Registers Introduction Table 11 lists the memory-mapped registers for the EMAC Control Module. See the device-specific data manual for the memory address of these registers. Offset Acronym EWCTL EWINTTCNT EMAC Control Module Interrupt Control Register (EWCTL) The EMAC control module interrupt control register (EWCTL) is used to enable and disable the central interrupt from the EMAC and MDIO modules.

  • Page 65: Emac Control Module Interrupt Timer Count Register (Ewinttcnt)

    www.ti.com EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) The EMAC control module interrupt timer count register (EWINTTCNT) is used to control the generation of back-to-back interrupts from the EMAC and MDIO modules. The value of this timer count is loaded into an internal counter every time interrupts are enabled using EWCTL.

  • Page 66: Mdio Registers

    MDIO Registers MDIO Registers Introduction Table 14 lists the memory-mapped registers for the Management Data Input/Output (MDIO). See the device-specific data manual for the memory address of these registers. Table 14. Management Data Input/Output (MDIO) Registers Offset Acronym VERSION CONTROL ALIVE LINK LINKINTRAW...

  • Page 67: Mdio Version Register (Version)

    www.ti.com MDIO Version Register (VERSION) The MDIO version register (VERSION) is shown in REVMAJ LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 15. MDIO Version Register (VERSION) Field Descriptions Field Value Description 31-16 MODID Identifies the type of peripheral 15-8 REVMAJ...

  • Page 68: Mdio Control Register (Control)

    MDIO Registers MDIO Control Register (CONTROL) The MDIO control register (CONTROL) is shown in IDLE ENABLE Reserved HIGHEST_USER_CHANNEL R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 16. MDIO Control Register (CONTROL) Field Descriptions Field Value Description...

  • Page 69: Phy Acknowledge Status Register (Alive)

    www.ti.com PHY Acknowledge Status Register (ALIVE) The PHY acknowledge status register (ALIVE) is shown in Figure 18. PHY Acknowledge Status Register (ALIVE) LEGEND: R/W = Read/Write; R/WC = Read/Write 1 to clear; -n = value after reset Table 17. PHY Acknowledge Status Register (ALIVE) Field Descriptions Field Value Description...

  • Page 70: Phy Link Status Register (Link)

    MDIO Registers PHY Link Status Register (LINK) The PHY link status register (LINK) is shown in LEGEND: R = Read only; -n = value after reset Table 18. PHY Link Status Register (LINK) Field Descriptions Field Value Description 31-0 LINK MDIO Link state bits.

  • Page 71: Mdio Link Status Change Interrupt (Unmasked) Register (Linkintraw)

    www.ti.com MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) The MDIO link status change interrupt (unmasked) register (LINKINTRAW) is shown in described in Table Figure 20. MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) LEGEND: R = Read only; R/WC = Read/Write 1 to clear; -n = value after reset Table 19.

  • Page 72: Mdio Link Status Change Interrupt (Masked) Register (Linkintmasked)

    MDIO Registers MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) The MDIO link status change interrupt (masked) register (LINKINTMASKED) is shown in described in Table Figure 21. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) LEGEND: R = Read only; R/WC = Read/Write 1 to clear; -n = value after reset Table 20.

  • Page 73: Mdio User Command Complete Interrupt (Unmasked) Register (Userintraw)

    www.ti.com MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) The MDIO user command complete interrupt (unmasked) register (USERINTRAW) is shown in and described in Table Figure 22. MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) LEGEND: R = Read only; R/WC = Read/Write 1 to clear; -n = value after reset Table 21.

  • Page 74: Mdio User Command Complete Interrupt (Masked) Register (Userintmasked)

    MDIO Registers MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) The MDIO user command complete interrupt (Masked) register (USERINTMASKED) is shown in Figure 23 and described in Table Figure 23. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) LEGEND: R = Read only; R/WC = Read/Write 1 to clear; -n = value after reset Table 22.

  • Page 75: Mdio User Command Complete Interrupt Mask Set Register (Userintmaskset)

    www.ti.com 4.10 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) The MDIO user command complete interrupt mask set register (USERINTMASKSET) is shown in Figure 24 and described in Table Figure 24. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) LEGEND: R = Read only;...

  • Page 76: Mdio User Command Complete Interrupt Mask Clear Register (Userintmaskclear)

    MDIO Registers 4.11 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in Figure 25 and described in Table Figure 25. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) LEGEND: R = Read only;...

  • Page 77: Mdio User Access Register 0 (Useraccess0)

    www.ti.com 4.12 MDIO User Access Register 0 (USERACCESS0) The MDIO user access register 0 (USERACCESS0) is shown in Figure 26. MDIO User Access Register 0 (USERACCESS0) WRITE Reserved R/WS-0 R/W-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; R/WS = Read/Write 1 to set; -n = value after reset Table 25.

  • Page 78: Mdio User Phy Select Register 0 (Userphysel0)

    MDIO Registers 4.13 MDIO User PHY Select Register 0 (USERPHYSEL0) The MDIO user PHY select register 0 (USERPHYSEL0) is shown in Figure 27. MDIO User PHY Select Register 0 (USERPHYSEL0) Reserved LEGEND: R = Read only; R/W = Read/Write; -n = value after reset Table 26.

  • Page 79: Mdio User Access Register 1 (Useraccess1)

    www.ti.com 4.14 MDIO User Access Register 1 (USERACCESS1) The MDIO user access register 1 (USERACCESS1) is shown in Figure 28. MDIO User Access Register 1 (USERACCESS1) WRITE Reserved R/WS-0 R/W-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; R/WS = Read/Write 1 to set; -n = value after reset Table 27.

  • Page 80: Mdio User Phy Select Register 1 (Userphysel1)

    MDIO Registers 4.15 MDIO User PHY Select Register 1 (USERPHYSEL1) The MDIO user PHY select register 1 (USERPHYSEL1) is shown in Figure 29. MDIO User PHY Select Register 1 (USERPHYSEL1) Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 28.

  • Page 81: Emac Port Registers

    www.ti.com EMAC Port Registers Introduction Table 29 lists the memory-mapped registers for the Ethernet Media Access Controller (EMAC). See the device-specific data manual for the memory address of these registers. Table 29. Ethernet Media Access Controller (EMAC) Registers Offset Acronym TXIDVER TXCONTROL TXTEARDOWN...
  • Page 82 EMAC Port Registers Table 29. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym 15Ch RX7FREEBUFFER 160h MACCONTROL 164h MACSTATUS 168h EMCONTROL 16Ch FIFOCONTROL 170h MACCONFIG 174h SOFTRESET 1D0h MACSRCADDRLO 1D4h MACSRCADDRHI 1D8h MACHASH1 1DCh MACHASH2 1E0h BOFFTEST 1E4h TPACETEST 1E8h RXPAUSE 1ECh...
  • Page 83 www.ti.com Table 29. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym 658h TX6CP 65Ch TX7CP 660h RX0CP 664h RX1CP 668h RX2CP 66Ch RX3CP 670h RX4CP 674h RX5CP 678h RX6CP 67Ch RX7CP 200h RXGOODFRAMES 204h RXBCASTFRAMES 208h RXMCASTFRAMES 20ch RXPAUSEFRAMES 210h RXCRCERRORS 214h...
  • Page 84 EMAC Port Registers Table 29. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym 270h FRAME128T255 274h FRAME256T511 278h FRAME512T1023 27Ch FRAME1024TUP 280h NETOCTETS 284h RXSOFOVERRUNS 288h RXMOFOVERRUNS 28Ch RXDMAOVERRUNS Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Register Description Transmit and Receive 128 to 255 Octet Frames Register Transmit and Receive 256 to 511 Octet Frames Register Transmit and Receive 512 to 1023 Octet Frames Register...

  • Page 85: Transmit Identification And Version Register (Txidver)

    www.ti.com Transmit Identification and Version Register (TXIDVER) The transmit identification and version register (TXIDVER) is shown in Table Figure 30. Transmit Identification and Version Register (TXIDVER) TXMAJORVER R-10 LEGEND: R = Read only; -n = value after reset Table 30. Transmit Identification and Version Register (TXIDVER) Field Descriptions Field Value Description...

  • Page 86: Transmit Control Register (Txcontrol)

    EMAC Port Registers Transmit Control Register (TXCONTROL) The transmit control register (TXCONTROL) is shown in Figure 31. Transmit Control Register (TXCONTROL) LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 31. Transmit Control Register (TXCONTROL) Field Descriptions Field Value Description...

  • Page 87: Transmit Teardown Register (Txteardown)

    www.ti.com Transmit Teardown Register (TXTEARDOWN) The transmit teardown register (TXTEARDOWN) is shown in Figure 32. Transmit Teardown Register (TXTEARDOWN) LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 32. Transmit Teardown Register (TXTEARDOWN) Field Descriptions Field Value Description...

  • Page 88: Receive Identification And Version Register (Rxidver)

    EMAC Port Registers Receive Identification and Version Register (RXIDVER) The receive identification and version register (RXIDVER) is shown in Table Figure 33. Receive Identification and Version Register (RXIDVER) RXMAJORVER R-10 LEGEND: R = Read only; -n = value after reset Table 33.

  • Page 89: Receive Control Register (Rxcontrol)

    www.ti.com Receive Control Register (RXCONTROL) The receive control register (RXCONTROL) is shown in Figure 34. Receive Control Register (RXCONTROL) LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 34. Receive Control Register (RXCONTROL) Field Descriptions Field Value Description...

  • Page 90: Receive Teardown Register (Rxteardown)

    EMAC Port Registers Receive Teardown Register (RXTEARDOWN) The receive teardown register (RXTEARDOWN) is shown in Figure 35. Receive Teardown Register (RXTEARDOWN) LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 35. Receive Teardown Register (RXTEARDOWN) Field Descriptions Field Value Description...

  • Page 91: Transmit Interrupt Status (Unmasked) Register (Txintstatraw)

    www.ti.com Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) The transmit interrupt status (unmasked) register (TXINTSTATRAW) is shown in Table Figure 36. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Reserved LEGEND: R = Read only; -n = value after reset Table 36. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions Field Value Description...

  • Page 92: Transmit Interrupt Status (Masked) Register (Txintstatmasked)

    EMAC Port Registers Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) The transmit interrupt status (Masked) register (TXINTSTATMASKED) is shown in described in Table Figure 37. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Reserved LEGEND: R/W = R = Read only; -n = value after reset Table 37.

  • Page 93: Transmit Interrupt Mask Set Register (Txintmaskset)

    www.ti.com 5.10 Transmit Interrupt Mask Set Register (TXINTMASKSET) The transmit interrupt mask set register (TXINTMASKSET) is shown in Table Figure 38. Transmit Interrupt Mask Set Register (TXINTMASKSET) Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 38.

  • Page 94: Transmit Interrupt Mask Clear Register (Txintmaskclear)

    EMAC Port Registers 5.11 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) The transmit interrupt mask clear register (TXINTMASKCLEAR) is shown in Table Figure 39. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 39.

  • Page 95: Mac Input Vector Register (Macinvector)

    www.ti.com 5.12 MAC Input Vector Register (MACINVECTOR) The MAC input vector register (MACINVECTOR) is shown in Figure 40. MAC Input Vector Register (MACINVECTOR) USER LINK RXPEND LEGEND: R = Read only; -n = value after reset Table 40. MAC Input Vector Register (MACINVECTOR) Field Descriptions Field Value Description...

  • Page 96: Receive Interrupt Status (Unmasked) Register (Rxintstatraw)

    EMAC Port Registers 5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) The receive interrupt status (Unmasked) register (RXINTSTATRAW) is shown in Table Figure 41. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Reserved LEGEND: R = Read only; -n = value after reset Table 41.

  • Page 97: Receive Interrupt Status (Masked) Register (Rxintstatmasked)

    www.ti.com 5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) The receive interrupt status (Masked) register (RXINTSTATMASKED) is shown in described in Table Figure 42. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Reserved LEGEND: R = Read only; -n = value after reset Table 42.

  • Page 98: Receive Interrupt Mask Set Register (Rxintmaskset)

    EMAC Port Registers 5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) The receive interrupt mask set register (RXINTMASKSET) is shown in Table Figure 43. Receive Interrupt Mask Set Register (RXINTMASKSET) Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 43.

  • Page 99: Receive Interrupt Mask Clear Register (Rxintmaskclear)

    www.ti.com 5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Table Figure 44. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Reserved LEGEND: R = Read only; R/W = Read/Write; R/WC = Read/Write 1 to clear; -n = value after reset Table 44.

  • Page 100: Mac Interrupt Status (Unmasked) Register (Macintstatraw)

    EMAC Port Registers 5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) The MAC interrupt status (unmasked) register (MACINTSTATRAW) is shown in Table Figure 45. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) LEGEND: R = Read only; -n = value after reset Table 45. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions Field Value Description...

  • Page 101: Mac Interrupt Status (Masked) Register (Macintstatmasked)

    www.ti.com 5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) The MAC interrupt status (masked) register (MACINTSTATMASKED) is shown in Table Figure 46. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) LEGEND: R/W = R = Read only; -n = value after reset Table 46. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions Field Value Description...

  • Page 102: Mac Interrupt Mask Set Register (Macintmaskset)

    EMAC Port Registers 5.19 MAC Interrupt Mask Set Register (MACINTMASKSET) The MAC interrupt mask set register (MACINTMASKSET) is shown in Table Figure 47. MAC Interrupt Mask Set Register (MACINTMASKSET) LEGEND: R = Read only; R/W = Read/Write; R/WS = Read/Write 1 to set; -n = value after reset Table 47.

  • Page 103: Mac Interrupt Mask Clear Register (Macintmaskclear)

    www.ti.com 5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) The MAC interrupt mask clear register (MACINTMASKCLEAR) is shown in Table Figure 48. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) LEGEND: R = Read only; R/W = Read/Write; R/WC = Read/Write 1 to clear; -n = value after reset Table 48.

  • Page 104: Receive Multicast/Broadcast/Promiscuous Channel Enable Register (Rxmbpenable)

    EMAC Port Registers 5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) The receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) is shown in Figure 49 and described in Table Figure 49. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Reserved RXPASSCRC RXQOSEN R/W-0 R/W-0 RXCSFEN RXCEFEN RXCAFEN R/W-0...
  • Page 105 www.ti.com Table 49. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Field Value Description RXCEFEN Receive copy error frames enable bit. Enables frames containing errors to be transferred to memory. The appropriate error bit will be set in the frame EOP buffer descriptor. Frames containing errors are filtered Frames containing errors are transferred to memory RXCAFEN...

  • Page 106: Receive Unicast Enable Set Register (Rxunicastset)

    EMAC Port Registers Table 49. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Field Value Description RXMULTCH 0-3h Receive multicast channel select Select channel 0 to receive multicast frames Select channel 1 to receive multicast frames Select channel 2 to receive promiscuous frames Select channel 3 to receive multicast frames Select channel 4 to receive multicast frames Select channel 5 to receive multicast frames...

  • Page 107: Receive Unicast Clear Register (Rxunicastclear)

    www.ti.com 5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) The receive unicast clear register (RXUNICASTCLEAR) is shown in Figure 51. Receive Unicast Clear Register (RXUNICASTCLEAR) Reserved RXCH7EN R/WC-0 LEGEND: R = Read only; R/W = Read/Write; R/WC = Read/Write 1 to clear; -n = value after reset Table 51.

  • Page 108: Receive Maximum Length Register (Rxmaxlen)

    EMAC Port Registers 5.24 Receive Maximum Length Register (RXMAXLEN) The receive maximum length register (RXMAXLEN) is shown in Figure 52. Receive Maximum Length Register (RXMAXLEN) LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 52. Receive Maximum Length Register (RXMAXLEN) Field Descriptions Field Value Description...

  • Page 109: Receive Buffer Offset Register (Rxbufferoffset)

    www.ti.com 5.25 Receive Buffer Offset Register (RXBUFFEROFFSET) The receive buffer offset register (RXBUFFEROFFSET) is shown in Figure 53. Receive Buffer Offset Register (RXBUFFEROFFSET) LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 53. Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions Field Value Description...

  • Page 110: Receive Filter Low Priority Frame Threshold Register (Rxfilterlowthresh)

    EMAC Port Registers 5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) The receive filter low priority frame threshold register (RXFILTERLOWTHRESH) is shown in and described in Table Figure 54. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 54.

  • Page 111: Receive Channel 0-7 Flow Control Threshold Register (Rxnflowthresh)

    www.ti.com 5.27 Receive Channel 0-7 Flow Control Threshold Register (RXnFLOWTHRESH) The receive channel 0-7 flow control threshold register (RXnFLOWTHRESH) is shown in described in Table Figure 55. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 55.

  • Page 112: Receive Channel 0-7 Free Buffer Count Register (Rxnfreebuffer)

    EMAC Port Registers 5.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER) The receive channel 0-7 free buffer count register (RXnFREEBUFFER) is shown in described in Table Figure 56. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) tLEGEND: R = Read only; R/W = Read/Write; WI = Write to increment; -n = value after reset Table 56.

  • Page 113: Mac Control Register (Maccontrol)

    www.ti.com 5.29 MAC Control Register (MACCONTROL) The MAC control register (MACCONTROL) is shown in Figure 57. MAC Control Register (MACCONTROL) Reserved RMIISPEED RXOFFLENBLOCK RXOWNERSHIP R/W-0 R/W-0 R/W-0 TXPACE GMIIEN R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 57.
  • Page 114 EMAC Port Registers Table 57. MAC Control Register (MACCONTROL) Field Descriptions (continued) Field Value CMDIDLE Reserved TXPTYPE Reserved TXPACE GMIIEN TXFLOWEN RXBUFFER FLOWEN Reserved LOOPBACK FULLDUPLEX Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) Description Receive flow control enabled. For full-duplex mode, outgoing pause frames are sent when receive FIFO flow control is triggered.

  • Page 115: Mac Status Register (Macstatus)

    www.ti.com 5.30 MAC Status Register (MACSTATUS) The MAC status register (MACSTATUS) is shown in IDLE TXERRCODE RXERRCODE Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 58. MAC Status Register (MACSTATUS) Field Descriptions Field Value Description IDLE...
  • Page 116 EMAC Port Registers Table 58. MAC Status Register (MACSTATUS) Field Descriptions (continued) Field Value Description 15-12 RXERRCODE Receive host error code. These bits indicate that EMAC detected receive DMA related host errors. The host should read this field after a host error interrupt (HOSTPEND) to determine the error. Host error interrupts require hardware reset in order to recover.

  • Page 117: Emulation Control Register (Emcontrol)

    www.ti.com 5.31 Emulation Control Register (EMCONTROL) The emulation control register (EMCONTROL) is shown in Figure 59. Emulation Control Register (EMCONTROL) LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 59. Emulation Control Register (EMCONTROL) Field Descriptions Field Value Description...

  • Page 118: Fifo Control Register (Fifocontrol)

    EMAC Port Registers 5.32 FIFO Control Register (FIFOCONTROL) The FIFO control register (FIFOCONTROL) is shown in Figure 60. FIFO Control Register (FIFOCONTROL) Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 60. FIFO Control Register (FIFOCONTROL) Field Descriptions Field Value Description...

  • Page 119: Mac Configuration Register (Macconfig)

    www.ti.com 5.33 MAC Configuration Register (MACCONFIG) The MAC configuration register (MACCONFIG) is shown in Figure 61. MAC Configuration Register (MACCONFIG) TXCELLDEPTH R-24 ADDRESSTYPE LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 61. MAC Configuration Register (MACCONFIG) Field Descriptions Field Value Description...

  • Page 120: Soft Reset Register (Softreset)

    EMAC Port Registers 5.34 Soft Reset Register (SOFTRESET) The Soft Reset Register (SOFTRESET) is shown in LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 62. Soft Reset Register (SOFTRESET) Field Descriptions Field Value Description 31-1 Reserved Reserved...

  • Page 121: Mac Source Address Low Bytes Register (Macsrcaddrlo)

    www.ti.com 5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) The MAC source address low bytes register (MACSRCADDRLO) is shown in Table Figure 63. MAC Source Address Low Bytes Register (MACSRCADDRLO) MACSRCADDR0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 63.

  • Page 122: Mac Source Address High Bytes Register (Macsrcaddrhi)

    EMAC Port Registers 5.36 MAC Source Address High Bytes Register (MACSRCADDRHI) The MAC Source Address High Bytes Register (MACSRCADDRHI) is shown in Table Figure 64. MAC Source Address High Bytes Register (MACSRCADDRHI) MACSRCADDR2 R/W-0 MACSRCADDR4 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 64.

  • Page 123: Mac Hash Address Register 1 (Machash1)

    www.ti.com 5.37 MAC Hash Address Register 1 (MACHASH1) The MAC hash registers allow group addressed frames to be accepted on the basis of a hash function of the address. The hash function creates a 6-bit data value (hash_fun) from the 48-bit destination address (DA) as follows: Hash_fun(0)=DA(0) XOR DA(6) XOR DA(12) XOR DA(18) XOR DA(24) XOR DA(30) XOR DA(36) XOR DA(42);...

  • Page 124: Mac Hash Address Register 2 (Machash2)

    EMAC Port Registers 5.38 MAC Hash Address Register 2 (MACHASH2) The MAC hash address register 2 (MACHASH2) is shown in Figure 66. MAC Hash Address Register 2 (MACHASH2) LEGEND: R/W = Read/Write; -n = value after reset Table 66. MAC Hash Address Register 2 (MACHASH2) Field Descriptions Field Value Description...

  • Page 125: Back Off Test Register (Bofftest)

    www.ti.com 5.39 Back Off Test Register (BOFFTEST) The back off test register (BOFFTEST) is shown in Figure 67. Back Off Random Number Generator Test Register (BOFFTEST) Reserved COLLCOUNT Reserved LEGEND: R = Read only; -n = value after reset Table 67. Back Off Test Register (BOFFTEST) Field Descriptions Field Value Description...

  • Page 126: Transmit Pacing Algorithm Test Register (Tpacetest)

    EMAC Port Registers 5.40 Transmit Pacing Algorithm Test Register (TPACETEST) The Transmit Pacing Algorithm Test Register (TPACETEST) is shown in Table Figure 68. Transmit Pacing Algorithm Test Register (TPACETEST) LEGEND: R = Read only; -n = value after reset Table 68. Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions Field Value Description...

  • Page 127: Receive Pause Timer Register (Rxpause)

    www.ti.com 5.41 Receive Pause Timer Register (RXPAUSE) The receive pause timer register (RXPAUSE) is shown in Figure 69. Receive Pause Timer Register (RXPAUSE) LEGEND: R = Read only; -n = value after reset Table 69. Receive Pause Timer Register (RXPAUSE) Field Descriptions Field Value Description...

  • Page 128: Transmit Pause Timer Register (Txpause)

    EMAC Port Registers 5.42 Transmit Pause Timer Register (TXPAUSE) The Transmit Pause Timer Register (TXPAUSE) is shown in Figure 70. Transmit Pause Timer Register (TXPAUSE) LEGEND: R = Read only; -n = value after reset Table 70. Transmit Pause Timer Register (TXPAUSE) Field Descriptions Field Value Description...

  • Page 129: Mac Address Low Bytes Register (Macaddrlo)

    www.ti.com 5.43 MAC Address Low Bytes Register (MACADDRLO) The MAC address low bytes register (MACADDRLO) is shown in Figure 71. MAC Address Low Bytes Register (MACADDRLO) Reserved MACADDR0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 71.

  • Page 130: Mac Address High Bytes Register (Macaddrhi)

    EMAC Port Registers 5.44 MAC Address High Bytes Register (MACADDRHI) The MAC address high bytes register (MACADDRHI) is shown in Figure 72. MAC Address High Bytes Register (MACADDRHI) MACADDR2 R/W-0 MACADDR4 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Table 72.

  • Page 131: Mac Index Register (Macindex)

    www.ti.com 5.45 MAC Index Register (MACINDEX) The MAC index register (MACINDEX) is shown in LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 73. MAC Index Register (MACINDEX) Field Descriptions Field Value Description 31-5 Reserved Reserved MACINDEX MAC address index.

  • Page 132: Transmit Channel 0-7 Dma Head Descriptor Pointer Register (Txnhdp)

    EMAC Port Registers 5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP) The transmit channel 0-7 DMA head descriptor pointer register (TXnHDP) is shown in described in Table Figure 74. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) LEGEND: R/W = Read/Write;...

  • Page 133: Receive Channel 0-7 Dma Head Descriptor Pointer Register (Rxnhdp)

    www.ti.com 5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RXnHDP) The receive channel 0-7 DMA head descriptor pointer register (RXnHDP) is shown in described in Table Figure 75. Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) LEGEND: R/W = Read/Write; -n = value after reset Table 75.

  • Page 134: Transmit Channel 0-7 Completion Pointer Register (Txncp)

    EMAC Port Registers 5.48 Transmit Channel 0-7 Completion Pointer Register (TXnCP) The Transmit Channel 0-7 Completion Pointer Register (TXnCP) is shown in Table Figure 76. Transmit Channel n Completion Pointer Register (TXnCP) LEGEND: R/W = Read/Write; -n = value after reset Table 76.

  • Page 135: Receive Channel 0-7 Completion Pointer Register (Rxncp)

    www.ti.com 5.49 Receive Channel 0-7 Completion Pointer Register (RXnCP) The receive channel 0-7 completion pointer register (RXnCP) is shown in Table Figure 77. Receive Channel n Completion Pointer Register (RXnCP) LEGEND: R/W = Read/Write; -n = value after reset Table 77. Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions Field Value Description...

  • Page 136: 5.50 Network Statistics Registers

    EMAC Port Registers 5.50 Network Statistics Registers The EMAC has a set of statistics that record events associated with frame traffic. The statistics values are cleared to zero 38 clocks after the rising edge of reset. When the GMIIEN bit in the MACCONTROL register is set, all statistics registers are write-to-decrement.
  • Page 137 www.ti.com 5.50.3 Multicast Receive Frames Register (RXMCASTFRAMES) The total number of good multicast frames received on the EMAC. A good multicast frame is defined as having all of the following: Any data or MAC control frame that was destined for any multicast address other than FF-FF-FF-FF-FF-FFh Was of length 64 to RXMAXLEN bytes inclusive Had no CRC error, alignment error, or code error...
  • Page 138 EMAC Port Registers 5.50.7 Receive Oversized Frames Register (RXOVERSIZED) The total number of oversized frames received on the EMAC. An oversized frame is defined as having all of the following: Was any data or MAC control frame that matched a unicast, broadcast, or multicast address, or matched due to promiscuous mode Was greater than RXMAXLEN in bytes Had no CRC error, alignment error, or code error...
  • Page 139 www.ti.com 5.50.11 Filtered Receive Frames Register (RXFILTERED) The total number of frames received on the EMAC that the EMAC address matching process indicated should be discarded. Such a frame is defined as having all of the following: Was any data frame (not MAC control frame) destined for any unicast, broadcast, or multicast address Did not experience any CRC error, alignment error, code error The address matching process decided that the frame should be discarded (filtered) because it did not match the unicast, broadcast, or multicast address, and it did not match due to promiscuous mode.
  • Page 140 EMAC Port Registers 5.50.15 Broadcast Transmit Frames Register (TXBCASTFRAMES) The total number of good broadcast frames transmitted on the EMAC. A good broadcast frame is defined as having all of the following: Any data or MAC control frame destined for address FF-FF-FF-FF-FF-FFh only Was of any length Had no late or excessive collisions, no carrier loss, and no underrun 5.50.16 Multicast Transmit Frames Register (TXMCASTFRAMES)
  • Page 141 www.ti.com 5.50.20 Transmit Single Collision Frames Register (TXSINGLECOLL) The total number of frames transmitted on the EMAC that experienced exactly one collision. Such a frame is defined as having all of the following: Was any data or MAC control frame destined for any unicast, broadcast, or multicast address Was any size Had no carrier loss and no underrun Experienced one collision before successful transmission.
  • Page 142 EMAC Port Registers 5.50.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE) The total number of frames on the EMAC that experienced carrier loss. Such a frame is defined as having all of the following: Was any data or MAC control frame destined for any unicast, broadcast, or multicast address Was any size The carrier sense condition was lost or never asserted when transmitting the frame (the frame is not re-transmitted)
  • Page 143 www.ti.com 5.50.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T511) The total number of 256-byte to 511-byte frames received and transmitted on the EMAC. Such a frame is defined as having all of the following: Any data or MAC control frame that was destined for any unicast, broadcast, or multicast address Did not experience late collisions, excessive collisions, underrun, or carrier sense error Was 256-bytes to 511-bytes long CRC errors, alignment/code errors, under-runs, and overruns do not affect the recording of frames in this...
  • Page 144 EMAC Port Registers 5.50.34 Receive FIFO or DMA Start of Frame Overruns Register (RXSOFOVERRUNS) The total number of frames received on the EMAC that had either a FIFO or DMA start of frame (SOF) overrun. An SOF overrun frame is defined as having all of the following: Was any data or MAC control frame that matched a unicast, broadcast, or multicast address, or matched due to promiscuous mode Was of any size (including less than 64-byte and greater than RXMAXLEN-byte frames)

  • Page 145: Appendix A Glossary

    www.ti.com Appendix A Glossary Broadcast MAC Address — A special Ethernet MAC address used to send data to all Ethernet devices on the local network. The broadcast address is FFh-FFh-FFh-FFh-FFh-FFh. The LSB of the first byte is odd, qualifying it as a group address; however, its value is reserved for broadcast. It is classified separately by the EMAC.

  • Page 146: Physical Layer Definitions

    Appendix A Jumbo Packets — Jumbo frames are defined as those packets whose length exceeds the standard Ethernet MTU, which is 1500 kbytes. For the C64x+ devices, it is recommended not to use packets exceeding 35K in length. The PHY that you use can place additional limits on to the length of the packets that you can transfer in a system.

  • Page 147: Appendix B Revision History

    www.ti.com Appendix B Revision History Table B-1 lists the changes made since the previous version of this document. Reference Additions/Modifications/Deletions Section 2.1 Changed Section Section 2.1.2 Changed Section Section 2.15.4 Changed Step Figure 3 Changed Figure Table 3 Changed Table 3 Figure 6 Changed Figure...
  • Page 148 TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:...

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