Bit Y/C Fifo Unpacking - Texas Instruments TMS320C64x DSP Reference Manual

Dsp video port/vcxo interpolated control (vic) port
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For 10-bit operation, two samples are unpacked from each FIFO word. This
is shown in Figure 4–17.
Figure 4–17. 10-Bit Y/C FIFO Unpacking
VCLKOUT
VDOUT[9–0]
Y 0
VDOUT[19–10]
Cb 0
63
5857
Y 15
Y 11
Y 7
Y 3
Y FIFO
63
5857
Cb 7
Cb 3
Cb FIFO
63
5857
Cr 7
Cr 3
Cr FIFO
63
5857
Y 12
Y 8
Y 4
Y 0
Y FIFO
63
5857
Cb 4
Cb 0
Cb FIFO
63
5857
Cr 4
Cr 0
Cr FIFO
SPRU629
Y 1
Y 2
Y 3
Y 4
Y 5
Cr 0
Cb 1
Cr 1
Cb 2
Cr 2
4847
4241
32
31
Y 14
Y 10
Y 6
Y 2
4847
4241
32
31
31
Cb 6
Cb 2
4847
4241
32
31
31
Cr 6
Cr 2
Little-Endian Unpacking
4847
4241
32
31
Y 13
Y 9
Y 5
Y 1
4847
4241
32
31
31
Cb 5
Cb 1
4847
4241
32
31
31
Cr 5
Cr 1
Big-Endian Unpacking
Y/C Video Display Mode
Y 6
Y 7
Y 8
Y 9
Y 10
Cb 3
Cr 3
Cb 4
Cr 4
Cb 5
2625
1615
10 9
Y 13
Y 9
Y 5
Y 1
2625
1615
10 9
Cb 5
Cb 1
2625
1615
10 9
Cr 5
Cr 1
2625
1615
10 9
Y 14
Y 10
Y 6
Y 2
2625
1615
10 9
Cb 6
Cb 2
2625
1615
10 9
Cr 6
Cr 2
Video Display Port
Y 11
Cr 5
0
Y 12
Y 8
Y 4
Y 0
0
Cb 4
Cb 0
0
Cr 4
Cr 0
0
Y 15
Y 11
Y 7
Y 3
0
Cb 7
Cb 3
0
Cr 7
Cr 3
4-19

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