Bit Raw Video Display Fifo Configuration - Texas Instruments TMS320C64x DSP Reference Manual

Video Port FIFO
For 8/10-bit raw video, the FIFO is configured as a single buffer as shown in
Figure 1–7. The FIFO outputs data on the VDOUT[9–0] half of the bus. The
FIFO has a single read pointer and write register (YDSTA).
Figure 1–7. 8/10-Bit Raw Video Display FIFO Configuration
YDSTA
For locked raw video, the FIFO is split into channel A and B. The channels are
locked together and use the same clock and control signals. Each channel
uses a single buffer and write register (YDSTx) as shown in Figure 1–8.
1-10 Overview
Display FIFO
64
Data Buffer
(5120 bytes)
VDOUT[9–0]
8/10
SPRU629