Video Port Pin Data Clear Register (Pdclr) Field Descriptions - Texas Instruments TMS320C64x DSP Reference Manual

GPIO Registers
Table 5–9. Video Port Pin Data Clear Register (PDCLR) Field Descriptions
†
Bit field symval
31–23 Reserved –
22 PDCLR22
NONE
VCTL3CLR
21 PDCLR21
NONE
VCTL2CLR
20 PDCLR20
NONE
VCTL1CLR
19–0 PDCLR[19–0]
NONE
VDATAnCLR
† For CSL implementation, use the notation VP_PDCLR_PDCLRn_symval
5-18 General Purpose I/O Operation
†
Value Description
0 Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
Allows PDOUT22 bit to be cleared to a logic low without
affecting other I/O pins controlled by the same port.
0 No effect.
1 Clears PDOUT22 (VCTL3) bit to 0.
Allows PDOUT21 bit to be cleared to a logic low without
affecting other I/O pins controlled by the same port.
0 No effect.
1 Clears PDOUT21 (VCTL2) bit to 0.
Allows PDOUT20 bit to be cleared to a logic low without
affecting other I/O pins controlled by the same port.
0 No effect.
1 Clears PDOUT20 (VCTL1) bit to 0.
Allows PDOUT[19–0] bit to be cleared to a logic low without
affecting other I/O pins controlled by the same port.
0 No effect.
1 Clears PDOUT[n] (VDATA[n]) bit to 0.
SPRU629