Texas Instruments TMS320C64x DSP Reference Manual page 251

GPIO Registers
Table 5–5. Video Port Pin Direction Register (PDIR) Field Descriptions (Continued)
†
Bit field symval
8 PDIR8
VDATA8TO9IN
VDATA8TO9OUT
7–5 Reserved –
4 PDIR4
VDATA4TO7IN
VDATA4TO7OUT
3–1 Reserved –
0 PDIR0
VDATA0TO3IN
VDATA0TO3OUT
† For CSL implementation, use the notation VP_PDIR_field_symval
5-10 General Purpose I/O Operation
†
Value Description
PDIR8 bit controls the direction of the VDATA[9–8] pins.
0 Pins function as input.
1 Pins function as output.
0 Reserved. The reserved bit location is always read as 0.
A value written to this field has no effect.
PDIR4 bit controls the direction of the VDATA[7–4] pins.
0 Pins function as input.
1 Pins function as output.
0 Reserved. The reserved bit location is always read as 0.
A value written to this field has no effect.
PDIR0 bit controls the direction of the VDATA[3–0] pins.
0 Pins function as input.
1 Pins function as output.
SPRU629