Table of Contents
Advertisement
Video Display Field and Frame Operation
4.7 Video Display Field and Frame Operation
As a video source, the video port always outputs entire frames of data and
transmits continuous video control signals. Depending on the DMA structure,
however, the video port may need to interrupt the DSP on a field or frame basis
to allow it to update video port registers or DMA parameters. To achieve this,
the video port provides programmable control over the display process.
4.7.1
Display Determination and Notification
In order to accommodate various display scenarios, DMA structures, and
processing flows, the video port employs a flexible display and DSP notifica-
tion system. This is programmed using the CON, FRAME, DF1, and DF2 bits
in VDCTL.
The CON bit controls the display of multiple fields or frames. When CON = 1,
continuous display is enabled, the video port displays outgoing fields (assuming
the VDEN bit is set) without the need for DSP interaction. It relies on a single
display buffer in memory or on a DMA structure with circular buffering capabili-
ty to service the display FIFOs. When CON = 0, continuous display is
disabled, the video port sets a field or frame display complete bit (F1D, F2D,
or FRMD) in VDSTAT upon the display of each field as determined by the state
of the other display control bits (FRAME, CD1, and CD2). Once the display
complete bit is set, the processor must update the appropriate DMA parameters
within the allotted time frame or a subsequent field or frame may output invalid
data. In this case, the video port continues to generate DMA requests but it
issues a DCNA (display complete not acknowledged) interrupt to indicate that
the DMA parameters may not have been updated and bad data is being sent
to the video port.
When a field or frame has not been enabled for display, no DMA events are
sent for that field or frame. The video port still generates all timings for the field
but outputs the default data values rather than data from the display FIFO
during the display image window.
The CON, FRAME, DF1, and DF2 bits encode the display operations as listed
in Table 4–4.
4-30
Video Display Port
SPRU629
Advertisement
Table of Contents
