Field Descriptions - Texas Instruments TMS320C64x DSP Reference Manual

Dsp video port/vcxo interpolated control (vic) port
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Table 3–15. Video Capture Channel A Control Register (VCACTL)
Field Descriptions (Continued)
Bit
field
symval
6
FRAME
NONE
FRMCAP
5
CF2
NONE
FLDCAP
4
CF1
NONE
FLDCAP
3
Reserved –
2–0
CMODE
BT656B
BT656D
RAWB
RAWD
YCB
YCD
RAW16
RAW20
† For CSL implementation, use the notation VP_VCACTL_field_symval
‡ For complete encoding of these bits, see Table 3–6, Table 3–11, and Table 3–12.
SPRU629
Value
BT.656 or Y/C Mode
Capture frame (data) bit.
0
Do not capture frame.
1
Capture frame.
Capture field 2 bit.
0
Do not capture field 2.
1
Capture field 2.
Capture field 1 bit.
0
Do not capture field 1.
1
Capture field 1.
0
Reserved. The reserved bit location is always read as 0. A value
written to this field has no effect.
Capture mode select bit.
0
Enables 8-bit BT.656 mode.
1h
Enables 10-bit BT.656 mode.
2h
Enables 8-bit raw data mode.
3h
Enables 10-bit raw data mode.
4h
Enables 16-bit Y/C mode.
5h
Enables 20-bit Y/C mode.
6h
Enables 16-bit raw mode.
7h
Enables 20-bit raw mode.
Video Capture Registers
Description
Raw Data Mode
TSI Mode
Do
not
capture
Do not capture
single data block.
single packet.
Capture single
Capture single
data block.
packet.
Do not capture
Not used.
field 2.
Capture field 2.
Not used.
Do not capture
Not used.
field 1.
Capture field 1.
Not used.
Not used.
Not used.
8-bit TSI mode.
Not used.
Not used.
Not used.
Not used.
Not used.
Video Capture Port
3-57

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