5.1.8
Video Port Pin Data Clear Register (PDCLR)
The video port pin data clear register (PDCLR) is shown in Figure 5–8 and
described in Table 5–9. PDCLR is an alias of the video port pin data output reg-
ister (PDOUT) for writes only and provides an alternate means of driving GPIO
outputs low. Writing a 1 to a bit of PDCLR clears the corresponding bit in
PDOUT. Writing a 0 has no effect. Register reads return all 0s.
Figure 5–8. Video Port Pin Data Clear Register (PDCLR)
31
23
22
Reserved
PDCLR22
R-0
W-0
15
14
PDCLR15
PDCLR14
W-0
W-0
7
6
PDCLR7
PDCLR6
W-0
W-0
Legend: R = Read only; W = Write only; -n = value after reset
SPRU629
Reserved
R-0
21
20
PDCLR21
PDCLR20
PDCLR19
W-0
W-0
13
12
PDCLR13
PDCLR12
PDCLR11
W-0
W-0
5
4
PDCLR5
PDCLR4
PDCLR3
W-0
W-0
19
18
17
PDCLR18
PDCLR17
W-0
W-0
W-0
11
10
PDCLR10
PDCLR9
W-0
W-0
W-0
3
2
PDCLR2
PDCLR1
W-0
W-0
W-0
General Purpose I/O Operation
GPIO Registers
24
16
PDCLR16
W-0
9
8
PDCLR8
W-0
1
0
PDCLR0
W-0
5-17