Texas Instruments SM320F2812-HT Data Manuals

Texas Instruments SM320F2812-HT Data Manuals

Manuals and User Guides for Texas Instruments SM320F2812-HT Data. We have 1 Texas Instruments SM320F2812-HT Data manual available for free PDF download: Data Manual

Texas Instruments SM320F2812-HT Data Data Manual

Texas Instruments SM320F2812-HT Data Data Manual (153 pages)

Digital Signal Processor

Brand: Texas Instruments | Category: Signal Processors | Size: 1.42 MB

Table of Contents

Table of Contents
2
Www.ti.com SGUS062B – JUNE 2009 – REVISED JUNE
9
1 Features

11
- Supports Extreme Temperature Applications
  12
2 Introduction

13
- Description
  13
- Device Summary
  13
- Hardware Features
  13
  - Die Layout
    14
- SM320F2812 die Layout
  14
- Bare die Information
  14
  - Pin Assignments
    15
- SM320F2812 172-Pin HFG CQFP (Top View)
  15
  - Signal Descriptions
    16
3 Functional Overview

25
- Memory Map
  26
- Functional Block Diagram
  26
- F2812 Memory Map (See Notes A. through G.)
  26
- Addresses of Flash Sectors in F2812
  27
- Wait States
  28
  - Brief Descriptions
    29
    
    C28X CPU
    29
    
    Memory Bus (Harvard Bus Architecture)
    29
    
    Peripheral Bus
    29
    
    Real-Time JTAG and Analysis
    29
    
    External Interface (XINTF)
    30
    
    Flash
    30
    
    L0, L1, H0 Sarams
    30
    
    Boot ROM
    30
    
    Security
    31
- Boot Mode Selection
  31
  - Peripheral Interrupt Expansion (PIE) Block
    32
  - External Interrupts (XINT1, XINT2, XINT13, XNMI)
    32
  - Oscillator and PLL
    32
  - Watchdog
    32
  - Peripheral Clocking
    32
  - Low-Power Modes
    32
  - Peripheral Frames 0, 1, 2 (Pfn)
    33
  - General-Purpose Input/Output (GPIO) Multiplexer
    33
  - 32-Bit CPU Timers (0, 1, 2)
    33
  - Control Peripherals
    33
  - Serial Port Peripherals
    34
  - Register Map
    34
- Peripheral Frame 0 Registers
  35
- Peripheral Frame 1 Registers
  35
- Peripheral Frame 2 Registers
  36
  - Device Emulation Registers
    37
  - External Interface, XINTF
    37
- External Interface Block Diagram
  38
  - Timing Registers
    39
  - XREVISION Register
    39
- XINTF Configuration and Control Register Mappings
  39
- XREVISION Register Bit Definitions
  39
  - Interrupts
    40
- Interrupt Sources
  40
- Multiplexing of Interrupts Using the PIE Block
  41
- PIE Peripheral Interrupts
  41
- PIE Configuration and Control Registers
  42
  - External Interrupts
    43
- External Interrupts Registers
  43
  - System Control
    44
- Clock and Reset Domains
  44
- PLL, Clocking, Watchdog, and Low-Power Mode Registers
  45
  - OSC and PLL Block
    46
- PLLCR Register Bit Definitions
  46
- Recommended Crystal/Clock Connection
  47
- Possible PLL Configuration Modes
  47
  - Watchdog Block
    48
- Watchdog Module
  48
  - Low-Power Modes Block
    49
- F2812 Low-Power Modes
  49
4 Peripherals

50
5 Development Support

80
6 Electrical Specifications

84
7 Mechanical Data

148
Revision History

149
- Www.ti.com SGUS062B – JUNE 2009 – REVISED JUNE
  149

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