Video Port Peripheral Control Register (Pcr) Field Descriptions - Texas Instruments TMS320C64x DSP Reference Manual

Table 5–3. Video Port Peripheral Control Register (PCR) Field Descriptions
†
Bit field symval
31–3 Reserved
2 PEREN
DISABLE
ENABLE
1 SOFT
STOP
COMP
0 FREE
SOFT
† For CSL implementation, use the notation VP_PCR_field_symval
SPRU629
†
Value Description
Reserved. The reserved bit location is always read as 0. A value
written to this field has no effect.
Peripheral enable bit.
0 Video port is disabled. Port clock (VCLK1, VCLK2, STCLK) inputs
are gated off to save power. DMA access to the video port is still
acknowledged but indeterminate read data is returned and write
data is discarded.
1 Video port is enabled.
Soft bit enable mode bit. This bit is used in conjunction with FREE
bit to determine state of video port clock during emulation suspend.
This bit has no effect if FREE = 1.
0 The current field is completed upon emulation suspend. After
completion, no new DMA events are generated. The port clocks
and counters continue to run in order to maintain synchronization.
No interrupts are generated. If the port is in display mode, video
control signals continue to be output and the default data value is
output during the active video window.
1 Is not defined for this peripheral; the bit is hardwired to 0.
Free-running enable mode bit. This bit is used in conjunction with
SOFT bit to determine state of video port during emulation suspend.
0 Free-running mode is disabled. During emulation suspend, SOFT
bit determines operation of video port.
1 Free-running mode is enabled. Video port ignores the emulation
suspend signal and continues to function as normal.
GPIO Registers
General Purpose I/O Operation 5-5