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GPIO Registers
5.1.4
Video Port Pin Direction Register (PDIR)
The video port pin direction register (PDIR) is shown in Figure 5–4 and
described in Table 5–5. The PDIR controls the direction of IO pins in the video
port for those pins set by PFUNC. If a bit is set to 1, the relevant pin or pin group
acts as an output. If a bit is cleared to 0, the pin or pin group functions as an
input. The PDIR settings do not affect pins where the corresponding PFUNC
bit is not set.
Figure 5–4. Video Port Pin Direction Register (PDIR)
31
23
22
Reserved
PDIR22
R-0
R/W-0
15
Reserved
R-0
7
Reserved
R-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 5–5. Video Port Pin Direction Register (PDIR) Field Descriptions
†
Bit
field
symval
31–23 Reserved –
22
PDIR22
VCTL3IN
VCTL3OUT
† For CSL implementation, use the notation VP_PDIR_field_symval
5-8
General Purpose I/O Operation
Reserved
R-0
21
20
19
PDIR21
PDIR20
R/W-0
R/W-0
13
12
PDIR12
Reserved
R/W-0
5
4
3
PDIR4
R/W-0
†
Value
Description
0
Reserved. The reserved bit location is always read as 0.
A value written to this field has no effect.
PDIR22 bit controls the direction of the VCTL3 pin.
0
Pin functions as input.
1
Pin functions as output.
Reserved
R-0
11
10
9
PDIR10
Reserved
R-0
R/W-0
R-0
Reserved
R-0
24
17
16
PDIR16
R/W-0
8
PDIR8
R/W-0
1
0
PDIR0
R/W-0
SPRU629
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