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Texas Instruments TMS320C6000 Technical Reference Manual

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Download this manual See also: Reference Manual, User Manual
TMS320C6000 Instruction Set Simulator
Technical Reference Manual
Literature Number: SPRU600I
April 2007

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Summary of Contents for Texas Instruments TMS320C6000

  • Page 1 TMS320C6000 Instruction Set Simulator Technical Reference Manual Literature Number: SPRU600I April 2007...
  • Page 2 SPRU600I – April 2007 Submit Documentation Feedback...

  • Page 3: Table Of Contents

    Contents ..........................Preface ..............Introduction to the TMS320C6000 Simulator ......................Features ............Supported Processors and Simulator Configurations ..............Considerations for Choosing a Simulator ................Supported Hardware Resources ......................1.4.1 ....................1.4.2 Memory ....................1.4.3 Peripherals .................. Supported Simulation Features ................
  • Page 4 ..................3.4.1 Supported Features ..................3.4.2 Known Limitations ......C6411/C6412/C6414/C6415/C6416/DM642 Device Cycle Accurate Simulators ..................3.5.1 Supported Features ..................3.5.2 Known Limitations ........DM6443/DM6446/C6455/TCI6482 Device Cycle Accurate Simulators ..................3.6.1 Supported Features ..................3.6.2 Known Limitations ..................Configuring the Simulator ..............
  • Page 5 TMS320C6211, C6711, C6712, and C6713 Device Cycle Accurate, and C6713 Device Functional ........................Simulators .......... Available Memory Ranges for Port Connect for TMS320C6000 Devices ............Available Pins for Configuration of the TMS320C6713 Device Available Pins for Configuration of TMS320C6202, C6203, C6412, C6414, C6415, C6416 and DM642 ........................
  • Page 6 List of Tables SPRU600I – April 2007 Submit Documentation Feedback...

  • Page 7: Preface

    TMS320C67x/67x+ DSPs. TMS320C6000 Peripherals Reference Guide (SPRU190) describes common peripherals available on the TMS320C6000 DSPs. This book includes information on the internal data and program memories, the external memory interface (EMIF), the host port, serial ports, direct memory access (DMA), enhanced direct memory access (EDMA), expansion bus (XBUS), clocking and phase-locked loop (PLL), and the power-down modes.
  • Page 8 www.ti.com Read This First SPRU600I – April 2007 Submit Documentation Feedback...

  • Page 9: Introduction To The Tms320C6000 Simulator

    Chapter 1 SPRU600I – April 2007 Introduction to the TMS320C6000 Simulator The TMS320C6000™ Instruction Set Simulator, available within the Code Composer Studio™ Integrated Development Environment (IDE) for TMS320C6000, simulates the TMS320C62x™, TMS320C64x™, TMS320C64x+™, TMS320C672x™, TMS320C67x™ generations of devices. This chapter lists the TMS320C6000 devices supported by the simulator and provides information to help in the selection of the best simulator configuration.

  • Page 10: Features

    Features Features The C6000™ simulators support the following features: • TMS320C6000 CPU full instruction set architecture execution • Support for C62x™, C64x™, C64x+™, C672x™, and C67x™. Support for all devices is based on these cores. • Port Connect, which also supports external peripheral simulation •...

  • Page 11: Considerations For Choosing A Simulator

    Supported Hardware Resources The following sections provide a concise overview of the supported hardware resources for each of the simulator configurations. For more detailed information on simulator configurations, see Chapter SPRU600I – April 2007 Introduction to the TMS320C6000 Simulator Submit Documentation Feedback...

  • Page 12: Cpu

    For each of the device simulators and device cycle-accurate simulators, the cache and internal memory models match the cache and memory architecture specifications described in the TMS320C6000 Peripherals Reference Guide (SPRU190). They support standard cache behavior such as: LRU line replacement, direct mapping, set associativity, cache protocols for hit/miss service, snoops, and victims.

  • Page 13: Tms320C6211, C6711, C6712, And C6713 Device Cycle Accurate, And C6713 Device Functional Simulators

    Table 1-5. TMS320C6211, C6711, C6712, and C6713 Device Cycle Accurate, and C6713 Device Functional Simulators C6211 C6711 C6712 C6713 C6713 FUNC Internal Memory/Cache Model QDMA EDMA EMIF Interrupt Selector McBSP McASP Timer GPIO SPRU600I – April 2007 Introduction to the TMS320C6000 Simulator Submit Documentation Feedback...
  • Page 14 Introduction to the TMS320C6000 Simulator SPRU600I – April 2007 Submit Documentation Feedback...

  • Page 15: Supported Simulation Features

    Chapter 2 SPRU600I – April 2007 Supported Simulation Features This chapter provides a concise overview of the supported simulation features for each of the simulator configurations. For more detailed information on each configuration, Chapter ....................Topic Page ..........External Event and Data Simulation ...........

  • Page 16: External Event And Data Simulation

    Waveform pins are sensitive to both rising and falling edges. For example, CPU interrupt pins are sensitive to rising edges, while the clock input pins of the serial port (CLKX, CLKR) of the TMS320C6000 devices are sensitive to rising and falling edges. See the following tables for details on the various pins supported for the different simulator configurations.

  • Page 17: Available Pins For Configuration Of The Tms320C6713 Device

    www.ti.com External Event and Data Simulation Table 2-2. Available Pins for Configuration of the TMS320C6713 Device Description Type Non-maskable interrupt Pulse INT4 General purpose external interrupt pin Pulse INT5 General purpose external interrupt pin Pulse INT6 General purpose external interrupt pin Pulse INT7 General purpose external interrupt pin...

  • Page 18: Available Pins For Configuration Of Tms320C6202, C6203, C6412, C6414, C6415, C6416 And Dm642 Devices

    www.ti.com External Event and Data Simulation Table 2-3. Available Pins for Configuration of TMS320C6202, C6203, C6412, C6414, C6415, C6416 and DM642 Devices Description Type Non-maskable interrupt Pulse INT4 General purpose external interrupt pin Pulse INT5 General purpose external interrupt pin Pulse INT6 General purpose external interrupt pin...

  • Page 19: Available Pins For Configuration Of Tms320C6412, C6416, C6713, And Dm642 Device Functional Simulators

    www.ti.com External Event and Data Simulation Table 2-4. Available Pins for Configuration of TMS320C64x, C62x, C67x, and C672x CPU Cycle Accurate Simulators (continued) Description Type INT11 General purpose external interrupt pin Pulse INT12 General purpose external interrupt pin Pulse INT13 General purpose external interrupt pin Pulse INT14...

  • Page 20: Port Connect

    Similarly, data can be received by connecting some files at the memory-mapped locations for the serial port receive register in read mode. Available memory ranges on the TMS320C6000 devices, to which a file can be connected for reading/writing, are given in Table 2-7.
  • Page 21 External Event and Data Simulation Table 2-7. Available Memory Ranges for Port Connect for TMS320C6000 Devices (continued) Configuration File Available Memory Range C6414 Device Cycle Accurate Simulator 0x6000 0000 - 0x6FFF FFFF 0x8000 0000 - 0xBFFF FFFF DXR0, DRR0, DXR1, DRR1, DXR2, DRR2...

  • Page 22: Reserved Memory Access Detection

    www.ti.com Reserved Memory Access Detection 12346666 33449999 cb56aaaa 5656cccc 89897f7f 2.1.2.2 Reset On reset, all of the Read file pointers are rewound, and Write files are closed and reopened in write mode. Port Connect can occur through the Code Composer Studio command window, GEL commands, or through the Port Connect plug-in.

  • Page 23: Limitations

    www.ti.com CPU Resource Conflict Detection 2.2.4 Limitations This feature does not support the addition of any new reserved area ranges (through the Code Composer Studio Memory Map feature) in addition to the ones as that are reserved in the hardware. Neither does it allow for selective removal of any such reserved memory regions.

  • Page 24: Types Of Conflict Detected

    www.ti.com CPU Resource Conflict Detection 2.3.2 Types of Conflict Detected Simulators detect the following types of conflict: • Unit over usage (S, M, L, and D units) • XPath and T unit over usage • C67x multi-cycle unit usage constraints •...

  • Page 25: Simulator Analysis

    Simulator Analysis Simulator Analysis The TMS320C6000 Simulator Analysis allows you to set up and monitor the occurrence of specific events. Some of the simulated events are program cache miss, program cache hit, program fetch, program access block 0, and program access block 1. The Simulator Analysis plug-in reports the occurrence of particular system events so that you can accurately monitor and measure the performance of the program.

  • Page 26: Rewind

    www.ti.com Rewind 2.10 Rewind The following simulators under the Code Composer Studio environment support a feature called Rewind. Using Rewind, the past history of an application being executed can be viewed. This reduces the time required to debug an application. See the Rewind User’s Guide (SPRU713) for more details. •...

  • Page 27: Interrupt Latency Detection

    www.ti.com Interrupt Latency Detection 2.13 Interrupt Latency Detection This tool allows you to measure the worst-case interrupt latency of the code, including programming interrupt constraints such as disabling GIE/NMIE, and architectural behavior such as non-serviceability of interrupts in branch delay slots. While programming, you may find that the algorithm has a larger interrupt latency than quoted.
  • Page 28 www.ti.com Supported Simulation Features SPRU600I – April 2007 Submit Documentation Feedback...

  • Page 29: Detailed Capabilities Of Individual Configurations

    Chapter 3 SPRU600I – April 2007 Detailed Capabilities of Individual Configurations This chapter describes the capabilities and known limitations of each simulator configuration....................Topic Page ..C62x/C64x/C67x/C672x/C64x+ CPU Cycle Accurate Simulators ..... C6416/C6713/C6412/DM642 Device Functional Simulators ... C6201/C6202/C6203/C6204/C6205/C6701 Device Simulators ..

  • Page 30: C62X/C64X/C67X/C672X/C64X+ Cpu Cycle Accurate Simulators

    www.ti.com C62x/C64x/C67x/C672x/C64x+ CPU Cycle Accurate Simulators C62x/C64x/C67x/C672x/C64x+ CPU Cycle Accurate Simulators In the CPU cycle-accurate simulator configurations, only the CPU core is modeled, along with device timer support and a flat memory model for the full addressable space. These simulators can be used for algorithmic verification if the functionality of the device peripherals is not needed.

  • Page 31: Known Limitations

    www.ti.com C6416/C6713/C6412/DM642 Device Functional Simulators The C6416 Device Functional Simulator can be used to simulate C6414/15 devices functionally. The C6713 Device Functional Simulator can be used to simulate the C6711, C6712, and C6211 configurations functionally. The C6412 Device Functional Simulator can be used to simulate the C6411 configuration functionally.

  • Page 32: C6201/C6202/C6203/C6204/C6205/C6701 Device Simulators

    www.ti.com C6201/C6202/C6203/C6204/C6205/C6701 Device Simulators • Rewind Limitations – Only CPU simulators and Device Functional Simulators support this feature. – Boot loading: If you try to back-step through the code which is copied during boot-loading, the disassembly window shows only NOPs. As mentioned previously, simulations on these configurations are not expected to be cycle accurate.

  • Page 33: Supported Features

    www.ti.com C6411/C6412/C6414/C6415/C6416/DM642 Device Cycle Accurate Simulators 3.4.1 Supported Features The bootload feature is supported by the simulator. The C6x1x Device Cycle Accurate Simulators have the cycle-accurate CPU and the cycle-accurate Timer module. The L1 and L2 are also modeled accurately. The EDMA subsystem and the EMIFs, although not accurate, will take cycles proportional to what will be taken on design, depending on transfer types, memory parameters, etc.

  • Page 34: Dm6443/Dm6446/C6455/Tci6482 Device Cycle Accurate Simulators

    www.ti.com DM6443/DM6446/C6455/TCI6482 Device Cycle Accurate Simulators • EDMA – Event polarity in XDMA is not supported. Therefore, events are taken only in active high state. – Push Data Transfer feature is not supported. – The synchronization events DSPINT, GPIOINT, SD_INTA, SD_INTB, PCI, UREVT, and UXEVT are not modeled.

  • Page 35: Configuring The Simulator

    Chapter 4 SPRU600I – April 2007 Configuring the Simulator Simulators can be configured for different features though the Code Composer Studio Setup program. However, to modify the advanced options, you need to modify the base configuration file (see Section 4.11.) ....................

  • Page 36: Setting The Resource Conflict Detection Mode

    www.ti.com Setting the Resource Conflict Detection Mode Setting the Resource Conflict Detection Mode CPU Resource Conflict Detection is a feature that allows you to find any resource problem with the use of CPU registers and functional units. If you are confident that there is no resource conflict problem in the code, this feature can be turned off to further enhance simulation speed.

  • Page 37: Setting The Bootload

    www.ti.com Setting the Bootload Setting the Bootload 4.3.1 Bootload in C6x0x Device Simulators The following are the Bootmodes supported in the C6x0x Device Simulators: • ROM_8BIT • ROM_16BIT • ROM_32BIT The Bootmode for C6x0x Device Simulators is not configurable via the Code Composer Studio Setup interface.

  • Page 38: Setting The Emif And Cpu Clocks

    www.ti.com Setting the EMIF and CPU Clocks • Boot destination address (BOOT_DST_ADDR) • Boot size (in bytes) (BOOTSIZE) For example, the following configuration file snippet does a simple memcopy of 256 bytes from 0x90000000 to 0x00000000..MODULE C64Xplus; BOOTMODE QUICK; BOOT_SRC_ADDR 0x90000000;...

  • Page 39: How To Write An Xbar File

    www.ti.com Setting Up the McBSP XBAR The XBAR connectivity is specified in a XBAR data file. Section 4.6.2 describes the file format in detail. The path and file name of the XBAR data file must be included in a simulator base configuration file (see Section 4.11), which is selected in Code Composer Studio Setup.

  • Page 40: Format Of The Configuration File To Be Picked Up

    www.ti.com Setting Up the McASP XBAR 4.6.2 Format of the Configuration File to be Picked Up McBSP XBAR is not configurable via the Code Composer Studio Setup interface. You must manually add a MCBSP_XBAR_FILE entry in the desired simulator's base configuration file (see Section 4.11.) In the case of C6x0x devices, add the entry MCBSP_XBAR_FILE as follows (note that XBAR is not...

  • Page 41: Format Of The Configuration File To Be Picked Up

    www.ti.com Setting the Maximum Memory Usage Limit 4.7.1 Format of the Configuration File to be Picked Up McASP XBAR is not configurable via the Code Composer Studio Setup interface. You must manually add a MCASP_XBAR_FILE entry in the desired simulator's base configuration file (see Section 4.11.) In the case of C6x0x devices, add the entry MCASP_XBAR_FILE as follows (note that XBAR is not...

  • Page 42: Absolute Clock Cycle

    www.ti.com File Format for Pin Connect clock_cycle The CPU clock-cycle parameter specifies the intervals at which interrupts will occur. Clock cycles can be specified as absolute or relative. logic_value The logic-value parameter is valid only for the pins of waveform-type (e.g., the FSX0 pin in the C6201 simulator).

  • Page 43: File Format For Port Connect

    www.ti.com File Format for Port Connect 4.10 File Format for Port Connect The Port Connect file contains one or more lines. Each line contains less than 80 characters to represent one data value. The data in the Port Connect file is interpreted as hex data and can be specified with a preceding 0x or without.
  • Page 44 www.ti.com Configuring the Simulator SPRU600I – April 2007 Submit Documentation Feedback...

  • Page 45: Performance Numbers

    Chapter 5 SPRU600I – April 2007 Performance Numbers Table 5-1 shows the performance numbers of the simulator for different device configurations. These numbers were gathered on a PC with a 2.4-GHz Intel Pentium ® ® 4 processor and 512 MB of RAM. Table 5-1.
  • Page 46 www.ti.com Performance Numbers SPRU600I – April 2007 Submit Documentation Feedback...

  • Page 47: Cycle Accuracy

    Chapter 6 SPRU600I – April 2007 Cycle Accuracy This chapter describes how the TMS320C6000 simulators have been validated for cycle accuracy using a benchmark suite of applications....................Topic Page ..........C6000 Simulators Benchmarking ............Notes on Cycle Accuracy SPRU600I – April 2007...

  • Page 48: C6000 Simulators Benchmarking

    C6000 Simulators Benchmarking C6000 Simulators Benchmarking The TMS320C6000 simulators have been validated for cycle accuracy using a benchmark suite of applications. The measurements on Device Cycle Accurate Simulators have been carried out in the following categories: • CPU + L1Cache + SRAM •...

  • Page 49: Notes On Cycle Accuracy

    www.ti.com Notes on Cycle Accuracy Table 6-1. Benchmarking Data for C6000 Simulators (continued) Application/Kernel Used for Referenced Percent Variance Benchmarking Hardware Simulator Configuration in Cycle Numbers Memory Accesses using DMA (CPU + L1Cache + L2Cache + EDMA + EMIF) Image Analysis - Histogram Computation C6416 DSK C6416 Device Cycle Accurate Simulator 1.80...
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