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TMS320VC5509A Silicon Errata
3.13 Hardware Accelerator Advisories
Advisory HWA_1
Revision(s) Affected:
Details:
Assembler Notification: None
Workaround:
1.0 and 1.1
The pixel interpolation computation is wrong by one pixel unit in "Decoder" mode, when
"Rounding Mode" is set to zero and when half-pixel interpolation is performed in the middle of
four full-resolution pixels (i.e., in the middle of two rows of pixels).
In "Decoder" mode, the Pixel Interpolator data path is configured to deliver two interpolated
pixels per cycle. Each section of the data path implements the computations shown below,
normalized according to video decoding standards:
A + B + Rnd
U =
2
U and R results are interpolated from lines and columns, respectively. M is computed from two
following full-resolution pixels lines. Two U, R, or M results are computed during each cycle by
the data path, according to the instruction being executed by the accelerator for the M results
set (the results are denoted as M0 and M1). When "Rounding Mode" (Rnd in the above
picture) is set to 1, the faulty data path section is implemented, M0 = (A+B+C+D+2)/4, which
is the correct result; but when "Rounding Mode" is set to 0, the data path section implements
M0=(A+B+C+D)/4. This is not correct and generates a bit exactness issue. The M1 result is
always correct, regardless of the "Rounding Mode" state.
Do not use the PI data path in the "Decoder" software when computing M type points and
when software-rounding is needed. Instead, use a routine consisting of regular C55x
instruction combinations. This routine must be called from the point where the one using PI
HWA instructions is and should take the same parameters and data organization. Hence, the
new routine should perform following steps:
•
Unpack the pixels in the CPU
•
Diagonal interpolation
Pixel Interpolation Hardware Accelerator
A + B + C + D + 1 + Rnd
M =
4
A
B
U
M
R
C
D
SPRZ200E
B + D + Rnd
R =
2
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