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Video Display Registers
4.12.6 Video Display Field 1 Vertical Blanking End Register (VDVBLKE1)
The video display field 1 vertical blanking end register (VDVBLKE1) controls
the end of vertical blanking in field 1. The VDVBLKE1 is shown in Figure 4–44
and described in Table 4–11.
In raw data mode, VBLNK is deasserted whenever the frame line counter
(FLCOUNT) is equal to VBLNKYSTOP1 and the frame pixel counter (FPCOUNT)
is equal to VBLNKXSTOP1 (this is shown in Figure 4–6, page 4-7).
In
FLCOUNT = VBLNKYSTOP1
VBLNK output control is completely independent of the timing control codes.
The V bit in the EAV/SAV codes for field 1 is controlled by the VDVBIT1 register.
Figure 4–44. Video Display Field 1 Vertical Blanking End Register (VDVBLKE1)
31
28 27
Reserved
R-0
15
12 11
Reserved
R-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
4-64
Video Display Port
BT.656
and
Y/C
mode,
VBLNKYSTOP1
VBLNKXSTOP1
VBLNK
is
deasserted
and
FPCOUNT = VBLNKXSTOP1.
R/W-0
R/W-0
whenever
This
16
0
SPRU629
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