Video Capture Channel B Control Register (Vcbctl); Video Capture Channel B Control Register (Vcbctl) Field Descriptions; Field Descriptions - Texas Instruments TMS320C64x DSP Reference Manual

Video Capture Registers

3.13.10 Video Capture Channel B Control Register (VCBCTL)

Video capture is controlled by the video capture channel B control register
(VCBCTL) shown in Figure 3–38 and described in Table 3–23.
Figure 3–38. Video Capture Channel B Control Register (VCBCTL)
31 30 29
RSTCH BLKCAP
R/WS-0 R/W-1
23
Reserved
R-0
15 14
VCEN PK10B
R/W-0 R/W-0
7 6
CON FRAME
R/W-0 R/W-0
Legend: R = Read only; R/W = Read/Write; WS = Write 1 to reset, write of 0 has no effect; -n = value after reset
Table 3–23. Video Capture Channel B Control Register (VCBCTL)

Field Descriptions

†
Bit field symval
31 RSTCH
NONE
RESET
† For CSL implementation, use the notation VP_VCBCTL_field_symval
‡ For complete encoding of these bits, see Table 3–6, Table 3–11, and Table 3–12.
3-68 Video Capture Port
21 20 19
FINV
R/W-0
13 12
LFDE
R/W-0
5 4 3
CF2 CF1
R/W-1 R/W-1
†
Value BT.656 or Y/C Mode
Reset channel bit. Write 1 to reset the bit, a write of 0 has no
effect.
0 No effect.
1 Resets the channel by blocking further DMA event generation
and flushing the FIFO upon completion of any pending DMAs.
Also clears the VCEN bit. All channel registers are set to their
initial values. RSTCH is autocleared after channel reset is complete.
Reserved
R-0
18
Reserved VRST
R-0 R/W-1
11 10
SFDE RESMPL Reserved
R/W-0 R/W-0
2 1
Reserved
R-0
Description
Raw Data Mode
24
17 16
HRST
R/W-0
9 8
SCALE
R-0 R/W-0
0
CMODE
R/W-0
TSI Mode
SPRU629