Clocks, Frames, And Data; Frame And Clock Operation; Clock And Frame Generation - Texas Instruments TMS320C6000 Reference Manual

Figure 2.

Frame and Clock Operation

CLK(R/X)
FS(R/X)
D(R/X) A1 A0
4

Clocks, Frames, and Data

Figure 3.

Clock and Frame Generation

CLKXM
CLKX pin
CLKXP
CLKRP
CLKRM
CLKR pin
CLKRP
internal clock source
FSR_int
CLKS pin
†
Internal clock source:
CPU clock for C620x/C670x
CPU/2 clock for C621x/C671x
CPU/4 clock for C64x DSP
SPRU580C
Á Á Á
Á Á Á
The McBSP has several ways of selecting clocking and framing for both the
receiver and transmitter. Clocking and framing can be sent to both portions by
the sample rate generator. Each portion can select external clocking and/or
framing independently. Figure 3 is a block diagram of the clock and frame
selection circuitry.
Clock selection
CLKXP
See inset See inset
CLKX_int
0
1
CLKXM
See inset
1
0
0
1
DLB
CLKRM
CLKR_int
CLKG
†
DSP
DSP
B7 B6 B5 B4
FSXP
See inset
FSX_int
0
Transmit
1
FSXM
FSGM
See inset
1
Receive
0
0
1
DLB
FSR_int FSRM
FSG
Sample
rate
generator
Multichannel Buffered Serial Port (McBSP)
Clocks, Frames, and Data
Á Á
B3 B2 B1 B0
Á Á
Frame selection
FSXM
FSXP
DXR to XSR
0
FSRP
FSRM and GSYNC
1
FSRP
Inset:
(R/X) IOEN
Yyy_int
FSX pin
FSR pin
19