Table of Contents
Advertisement
www.ti.com
NAME
Device Emulation Registers
reserved
(3)
FLASH Registers
Code Security Module Registers
reserved
XINTF Registers
reserved
CPU-TIMER0/1/2 Registers
reserved
PIE Registers
PIE Vector Table
Reserved
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) If registers are EALLOW protected, then writes cannot be performed until the user executes the EALLOW instruction. The EDIS
instruction disables writes. This prevents stray code or pointers from corrupting register contents.
(3) The Flash Registers are also protected by the Code Security Module (CSM).
NAME
eCAN Registers
eCAN Mailbox RAM
reserved
(1) The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries.
Copyright © 2009–2011, Texas Instruments Incorporated
Table 3-4. Peripheral Frame 0 Registers
ADDRESS RANGE
0x00 0880
0x00 09FF
0x00 0A00
0x00 0A7F
0x00 0A80
0x00 0ADF
0x00 0AE0
0x00 0AEF
0x00 0AF0
0x00 0B1F
0x00 0B20
0x00 0B3F
0x00 0B40
0x00 0BFF
0x00 0C00
0x00 0C3F
0x00 0C40
0x00 0CDF
0x00 0CE0
0x00 0CFF
0x00 0D00
0x00 0DFF
0x00 0E00
0x00 0FFF
Table 3-5. Peripheral Frame 1 Registers
ADDRESS RANGE
0x00 6000
0x00 60FF
0x00 6100
0x00 61FF
0x00 6200
0x00 6FFF
Submit Documentation Feedback
Product Folder Link(s):
(1)
SIZE (×16)
384
128
96
16
48
32
192
64
160
32
256
512
(1)
SIZE (×16)
256
Some eCAN control registers (and selected bits in
(128 × 32)
other eCAN control registers) are EALLOW-protected.
256
Not EALLOW-protected
(128 × 32)
3584
SM320F2812-HT
SM320F2812-HT
SGUS062B – JUNE 2009 – REVISED JUNE 2011
(2)
ACCESS TYPE
EALLOW protected
EALLOW protected
CSM Protected
EALLOW protected
Not EALLOW protected
Not EALLOW protected
Not EALLOW protected
EALLOW protected
ACCESS TYPE
Functional Overview
35
Advertisement
Table of Contents
