How The I-Cache Uses The Fetch Address; Instruction Presence Check And The Corresponding I-Cache Response; Fetch Address Fields For The 2-Way Cache; Fetch Address Field Descriptions For The 2-Way Cache - Texas Instruments TMS320VC5501 Instruction Cache

1.2.1

How the I-Cache Uses the Fetch Address

Figure 3.

Fetch Address Fields for the 2-Way Cache

23
Tag
11 bits
Table 1.

Fetch Address Field Descriptions for the 2-Way Cache

Bit Field
23−13 Tag
12−4 Index
3−2 Offset
1−0 Byte
1.2.2

Instruction Presence Check and the Corresponding I-Cache Response

SPRU630C
Figure 3 and Table 1 describe how the I-Cache uses the fetch address for the
2-way cache.
13 12
Description
Whenever a line of the 2-way cache is loaded from external memory, the tag
portion of the fetch address is stored with the line (in the tag array). During an
instruction presence check, the I-Cache uses the Index field to find the
addressed set and then compares both tags in the set with the tag portion of the
fetch address.
This 9-bit value references one of the 512 sets of the 2-way cache. As shown in
Figure 2 (page 12), each set has two lines.
When the I-Cache must read a 32-bit word from one of the lines of the 2-way
cache, the offset field indicates which of the four 32-bit words in the line should
be read.
This field is not used by the I-Cache but is the part of the fetch address that
indicates the specific byte being addressed.
As mentioned earlier, when a fetch request arrives, the I-Cache performs an
instruction presence check to determine whether the 32-bit requested word is
available in the I-Cache. During the instruction presence check, the I-Cache
performs these two operations on the 2-way cache:
1) Compares the tag portion of the fetch address with the tag in the data array
at the location referenced by the Index portion of the fetch address.
2) Checks the line valid bit at the referenced location, to determine whether
the line associated with the tag is valid.
If the tag comparison fails and/or the line valid bit is 0, this qualifies as a miss.
If the instruction presence check finds a tag match and the line valid bit is 1,
this qualifies as a hit. Table 2 summarizes the possible presence check and
the corresponding I-Cache responses. Whenever a line in the I-Cache must
be loaded from external memory the I-Cache uses the line load process
described in section 1.2.3.
4
Index (set)
9 bits
Instruction Cache
Introduction
3 2 1 0
Offset Byte
2 bits 2 bits
13