Register Map; Peripheral Frame 0 Registers; Peripheral Frame 1 Registers - Texas Instruments TMS320C2810 Data Manual

www.ti.com
3.3

Register Map

The F281x and C281x devices contain three peripheral register spaces. The spaces are categorized as
follows:
Peripheral Frame 0:
Peripheral Frame 1:
Peripheral Frame 2:
NAME
Device Emulation Registers
Reserved
(3)
FLASH Registers
Code Security Module Registers
Reserved
XINTF Registers
Reserved
CPU-TIMER0/1/2 Registers
Reserved
PIE Registers
PIE Vector Table
Reserved
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) If registers are EALLOW protected, then writes cannot be performed until the user executes the EALLOW instruction. The EDIS
instruction disables writes. This prevents stray code or pointers from corrupting register contents.
(3) The Flash Registers are also protected by the Code Security Module (CSM).
NAME
eCAN Registers
eCAN Mailbox RAM
Reserved
(1) The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries.
Copyright © 2001–2012, Texas Instruments Incorporated
Product Folder Link(s):
These are peripherals that are mapped directly to the CPU memory bus.
See Table 3-6.
These are peripherals that are mapped to the 32-bit peripheral bus.
See Table 3-7.
These are peripherals that are mapped to the 16-bit peripheral bus.
See Table 3-8.
Table 3-6. Peripheral Frame 0 Registers
ADDRESS RANGE
0x00 0880 – 0x00 09FF
0x00 0A00 – 0x00 0A7F
0x00 0A80 – 0x00 0ADF
0x00 0AE0 – 0x00 0AEF
0x00 0AF0 – 0x00 0B1F
0x00 0B20 – 0x00 0B3F
0x00 0B40 – 0x00 0BFF
0x00 0C00 – 0x00 0C3F
0x00 0C40 – 0x00 0CDF
0x00 0CE0 – 0x00 0CFF
0x00 0D00 – 0x00 0DFF
0x00 0E00 – 0x00 0FFF
Table 3-7. Peripheral Frame 1 Registers
ADDRESS RANGE
0x00 6000 – 0x00 60FF
0x00 6100 – 0x00 61FF
0x00 6200 – 0x00 6FFF
Submit Documentation Feedback
TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174T – APRIL 2001 – REVISED MAY 2012
(1)
SIZE (x16)
384
128
96
16
48
32
192
64
160
32
256
512
(1)
SIZE (x16)
256 Some eCAN control registers (and selected bits in
(128 x 32) other eCAN control registers) are EALLOW-protected.
256
Not EALLOW-protected
(128 x 32)
3584
(2)
ACCESS TYPE
EALLOW protected
EALLOW protected
CSM Protected
EALLOW protected
Not EALLOW protected
Not EALLOW protected
Not EALLOW protected
EALLOW protected
ACCESS TYPE
Functional Overview 39