Processor Voltage Regulator Power Delivery Architectural Block Diagram; Customer Reference Board Power Delivery; Processor Voltage Regulator Block Diagram - Intel Pentium M Processor Design Manual

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Intel Pentium M Processor and Intel
Platform Power Delivery Guidelines
11.1 Processor Voltage Regulator Power Delivery
Architectural Block Diagram
Figure 126.

Processor Voltage Regulator Block Diagram

Clock
Driver
NOTES:
† Desired, but not required feature of a voltage regulator compliant controller. When not implemented by the
voltage regulator, both the CLK_ENABLE# and the t
control logic.
The voltage regulator receives three input power rails, VDC, V_5, and V_3. VDC is the main
power input to the system. VDC ranges between 5.5 – 21 V. V_5 is the output rail of the main 5.0 V
voltage regulator (VR). This rail is typically used to provide drive power to the MOSFET gate
driver. V_3 is the output rail of the 3.3 volt VR. This is typically used to provide power to the VR
Controller and miscellaneous logic and pull-ups.
11.2

Customer Reference Board Power Delivery

Figure 127
E7501 chipset customer reference board.
188
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E7501 Chipset Platform
VDC
Voltage
V_5
IMVP-IV
Regulator
V_3
1
CLK_ENABLE
Platform
Logic
shows the power delivery architecture for the Intel
PSI#
VID[5:0]
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Intel
V cc_core
PW RGOOD
VCCP
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Intel
ICH3-S
timer must be implemented by platform
CPU-PWRGD
2
Intel
Pentium
Processor
I/O
VCC
I/O I/O
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Intel
Intel
E7501
ICH3-S
Chipset
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Pentium M processor and Intel
Design Guide
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M
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