Clk-Synchronous Mode - Fujitsu F2MC-16LX Hardware Manual

17.4.3 CLK-synchronous Mode

In the CLK-synchronous mode, a synchronous clock for receiving data is generated
automatically if the internal clock is selected. A one-byte clock must be supplied if the
external clock is selected.
■ Transfer Data Format
The UART handles only data in NRZ (non return to zero) format. Figure 17.4-2 shows the
relationship between the transmitter or receiver clock and data.
Write into SODR
SCLK
RXE, TXE
SIN, SOT
If the internal clock (communication prescaler or internal timer) is selected, a synchronous clock
for receiving data is generated automatically when data is transmitted.
If the external clock is selected, the transmitter data buffer SODR register of the transmitter
UART is checked for data (TDRE flag is "0") and then a one-byte clock must be supplied
accurately. Set the mark level to H before and after transmission.
Only eight-bit data is valid and no parity bit can be added to data. No errors other than overrun
errors are detected because neither start bit nor stop bit is provided.
Figure 17.4-4 Transfer Data Format (Mode 2)
1 0 1
LSB
Transferred data is 01001101
1 0 0 1 0
MSB
.
B
17.4 UART Operations
Mark
(Mode 2)
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