Bus Integrity Test - Fujitsu FX-3001SR User Manual

Error messages
The register name and value of the error, and the register values for all the
banks are displayed.
Bank 0
zero clear ... success.
write 0x0000 ... success.
write 0xFFFF ... success.
write 0xAAAA ... success.
write 0x5555 ... success.
Bank 1
zero clear ...
IA0-1 reg unmatch 0x0000 ===> 0xFFFF
Bank 0: 0x1505 0x0000 0x4105 0x0000 0x0404 0x1054 0x0000 0x3300
Bank 1: 0x20B1 0x1801 0xFFFF 0x0000 0x0000 0x0000 0x1210 0x3301
Bank 2: 0x3332 0x8000 0x8080 0x0000 0x5555 0x5555 0x0004 0x3302
Bank 3: 0x0000 0x0000 0x0000 0x0000 0x3330 0x3391 0x001F 0x3303
7.2.1.3.2

bus integrity test

This is a test designed to induce a bit error in the dependence/independence of the
address bus and data bus using a large amount of consecutive data such as 1, 0, 1,
0, etc. This is repeated 10 times.
Example
Bank 0 write 0xAAAA/0x5555 ... success.
Bank 1 write 0x5555/0xAAAA ... success.
Bank 2 write 0xAAAA/0x5555 ... success.
Bank 3 write 0x5555/0xAAAA ... success.
.
. (Omitted)
.
Bank 0 write 0xAAAA/0x5555 ... success.
Bank 1 write 0x5555/0xAAAA ... success.
Bank 2 write 0xAAAA/0x5555 ... success.
Bank 3 write 0x5555/0xAAAA ... success.
Bank 0 write 0x5555/0xAAAA ... success.
Bank 1 write 0xAAAA/0x5555 ... success.
Bank 2 write 0x5555/0xAAAA ... success.
Bank 3 write 0xAAAA/0x5555 ... success.
Error messages
The register name and value of the error, and the register values for all the
banks are displayed. Same as the data compare test.
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