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7.2.1.1.2
This is a test designed to induce a bit error in the dependence/independence of
the address bus and data bus using a large amount of consecutive data such as
1, 0, 1, 0, etc.
(1) Input format
Start address? [0x08000000:default, -1:top]
End
Specify a test start address and end address.
Same as the data compare test.
(2) Test results
The SDRAM control registers and test results are displayed as shown below.
Start address? [0x08000000:default, -1:top]
End
Output message to Local and Target Port? [Y/N] > Y
SDRAM Control Registers
7
SDCTL0
SDCTL1
MISCELLANEOUS 0x00221014:00000000
SDRST
Check SDRAM0
Test 0x08000000 - 0x09FFFFFF
write 0xAAAAAAAA/0x55555555 ...
verify ...
SDRAM0 check done.
Check SDRAM1
Test 0x0C000000 - 0x0DFFFFFF
write 0xAAAAAAAA/0x55555555 ...
verify ...
SDRAM1 check done.
Error messages
Same as the data compare test.
SERVIS IP-Serial
166
1p Converter
User's Guide
bus integrity test
address? [0x08FFFFFF:default, -1:bottom] >
address? [0x08FFFFFF:default, -1:bottom] > -1
0x00221000:81128300
0x00221004:81128300
0x00221018:00000000
>
> -1
Enter
Enter
Enter
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