Table 8-10. Reg Field; Table 8-11. Sreg2 Field Encoding; Table 8-12. Sreg3 Field (Fs And Gs Segment Register Selection) - AMD Geode LX 600@0.7W Data Book

33234H
8.1.4 reg Field
The reg field (Table 8-10) determines which general registers are to be used. The selected register is dependent on
whether a 16-bit or 32-bit operation is current and on the status of the w bit.
reg
000
001
010
011
100
101
110
111
8.1.4.1 sreg2 Field (ES, CS, SS, DS Register Selection)
The sreg2 field (Table 8-11) is a 2-bit field that allows one of the four 286-type segment registers to be specified.
sreg2 Field
00
01
10
11
8.1.4.2 sreg3 Field (FS and GS Segment Register Selection)
The sreg3 field (Table 8-12) is 3-bit field that is similar to the sreg2 field, but allows use of the FS and GS segment registers.

Table 8-12. sreg3 Field (FS and GS Segment Register Selection)

sreg3 Field
000
001
010
011
100
101
110
111
624

Table 8-10. reg Field

16-Bit Operation
w = 0 w = 1
AL AX
CL CX
DL DX
BL BX
AH SP
CH BP
DH
BH

Table 8-11. sreg2 Field Encoding

w = 0
AL
CL
DL
BL
AH
CH
SI DH
DI BH
Segment Register Selected
ES
CS
SS
DS
Segment Register Selected
ES
CS
SS
DS
FS
GS
Undefined
Undefined
Instruction Set
32-Bit Operation
w = 1
EAX
ECX
EDX
EBX
ESP
EBP
ESI
EDI
AMD Geode™ LX Processors Data Book