AMD Geode LX 600@0.7W Data Book page 198

33234H
5.5.2.108 Bus Controller Debug Register 6 MSR (BDR6_MSR)
MSR Address 00001976h
Type R/W
Reset Value 00000000_00000000h
This register contains the status of the bus controller breakpoints. When a breakpoint occurs, the corresponding status bit
is set in this register. The status bits remain set until cleared by an MSR write.
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Name
63:4 RSVD
3 T3
2 T2
1 T1
0 T0
5.5.2.109 Bus Controller Debug Register 7 MSR (BDR7_MSR)
MSR Address 00001977h
Type R/W
Reset Value 00000000_00000000h
This register is the bus controller breakpoint control/enable register.
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TYPE3 TYPE2
Bit Name
63:32 RSVD
198
BDR6_MSR Register Map
RSVD
RSVD
BDR6_MSR Bit Descriptions
Description
Reserved. (Default = 0)
Breakpoint 3 Triggered. A 1 Indicates that breakpoint 3 has triggered. Write to clear.
(Default = 0)
Breakpoint 2 Triggered. A 1 Indicates that breakpoint 2 has triggered. Write to clear.
(Default = 0)
Breakpoint 1 Triggered. A 1 Indicates that breakpoint 1 has triggered. Write to clear.
(Default = 0)
Breakpoint 0 Triggered. A 1 Indicates that breakpoint 0 has triggered. Write to clear.
(Default = 0)
BDR7_MSR Register Map
RSVD
TYPE1 TYPE0
BDR7_MSR Bit Descriptions
Description
Reserved. (Default = 0)
CPU Core Register Descriptions
9 8 7 6 5 4
T3 T2 T1 T0
9 8 7 6 5 4
RSVD E3 E2 E1 E0
AMD Geode™ LX Processors Data Book
3 2 1 0
3 2 1 0