AMD Geode LX 600@0.7W Data Book page 322

33234H
6.6.4.2 DC Compression Buffer Start Address (DC_CB_ST_OFFSET)
DC Memory Offset 014h
Type R/W
Reset Value xxxxxxxxh
This register specifies the offset at which the compressed display buffer starts. Settings written to this register do not take
effect until the start of the following frame or interlaced field.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RSVD
Bit Name
31:28 RSVD
27:0 OFFSET
6.6.4.3 DC Cursor Buffer Start Address (DC_CURS_ST_OFFSET)
DC Memory Offset 018h
Type R/W
Reset Value xxxxxxxxh
This register specifies the offset at which the cursor memory buffer starts. Settings written to this register do not take effect
until the start of the following frame or interlaced field.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RSVD
Bit Name
31:28 RSVD
27:0 OFFSET
322
DC_CB_ST_OFFSET Register Map
OFFSET
DC_CB_ST_OFFSET Bit Descriptions
Description
Reserved.
Compressed Display Buffer Start Offset. This value represents the byte offset of the
starting location of the compressed display buffer. The lower five bits should always be
programmed to zero so that the start offset is aligned to a 32-byte boundary. This value
should change only when a new display mode is set due to a change in size of the frame
buffer.
DC_CURS_ST_OFFSET Register Map
OFFSET
DC_CURS_ST_OFFSET Bit Descriptions
Description
Reserved.
Cursor Start Offset. This value represents the byte offset of the starting location of the
cursor display pattern. The lower five bits should always be programmed to zero so that
the start offset is 32-byte aligned. Note that if there is a Y offset for the cursor pattern, the
cursor start offset should be set to point to the first displayed line of the cursor pattern.
Display Controller Register Descriptions
9 8 7 6 5 4 3
9 8 7 6 5 4 3
AMD Geode™ LX Processors Data Book
2 1 0
0h
2 1 0
0h