AMD Geode LX 600@0.7W Data Book page 74

33234H
Bit Name
2 HIT_ASMI
1 HIT_DEC
0 HIT_LDEN
4.2.3.4 Request Compare Value (RQ_COMPARE_VAL[0:3]
The RQ Compare Value and the RQ Compare Mask enable traps on specific transactions. A hit to the RQ Compare is
determined by hit = (RQ_IN & RQ_COMPARE_MASK) == RQ_COMPARE_VAL). A hit can trigger the RQ_CMP error
sources when they are enabled. The value is compared only after the packet is arbitrated.
Request Compare Value (RQ_COMPARE_VAL[0])
MSR Address GLIU0: 100000C0h
GLIU1: 400000C0h
Type R/W
Reset Value 001FFFFF_FFFFFFFFh
Request Compare Value (RQ_COMPARE_VAL[1])
MSR Address GLIU0: 100000C2h
GLIU1: 400000C2h
Type R/W
Reset Value 001FFFFF_FFFFFFFFh
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Name
63:53 RSVD
52:0 RQ_VAL
74
STATISTIC_ACTION[0:3] Bit Descriptions
Description
Assert ASMI on Descriptor Hit. The descriptor hits are ANDed with the masks and then
all ORed together.
0: Disable.
1: Enable.
Decrement Counter on Descriptor Hit. The descriptor hits are ANDed with the masks
and then all ORed together.
0: Disable.
1: Enable.
Load Counter on Descriptor Hit. The descriptor hits are ANDed with the masks and
then all ORed together.
0: Disable.
1: Enable.
RQ_COMPARE_VAL[0:3] Register
RQ_VAL
RQ_COMPARE_VAL[0:3] Bit Descriptions
Description
Reserved.
Request Packet Value. This is the value compared against the logical bit-wise AND of
the incoming request packet and the RQ_COMPMASK in order to determine a 'hit".
Request Compare Value (RQ_COMPARE_VAL[2])
MSR Address GLIU0: 100000C4h
GLIU1: 400000C4h
Type R/W
Reset Value 001FFFFF_FFFFFFFFh
Request Compare Value (RQ_COMPARE_VAL[3])
MSR Address GLIU0: 100000C6h
GLIU1: 400000C6h
Type R/W
Reset Value 001FFFFF_FFFFFFFFh
RQ_VAL
9 8
AMD Geode™ LX Processors Data Book
GLIU Register Descriptions
7 6 5 4 3 2 1 0