Page 1 AMD Geode™ LX Processors Data Book February 2009 Publication ID: 33234H AMD Geode™ LX Processors Data Book...
Page 2 Contacts www.amd.com Trademarks AMD, the AMD Arrow logo, AMD Athlon, Geode, GeodeLink, 3DNow!, and combinations thereof, are trademarks of Advanced Micro Devices, Inc. Linux is a registered trademark of Linus Torvalds. WinBench is a registered trademark of Ziff Davis, Inc.
Page 3: Table Of Contents
CPU Core Register Descriptions ..........99 AMD Geode™ LX Processors Data Book...
Page 4 Processor Core Instruction Set ..........633 MMX™, FPU, and AMD 3DNow!™ Technology Instructions Sets ..... . 658 Package Specifications .
Page 5: List Of Figures
525 line, 60 Hz Digital Vertical Timing ......... 468 AMD Geode™ LX Processors Data Book...
Page 6 AMD Geode™ LX Processors OPN Example ........
Page 7: List Of Tables
LUT (Lookup Table) Load Command Buffer Structure ......240 AMD Geode™ LX Processors Data Book...
Page 8 VOP Clock Rate ............404 List of Tables AMD Geode™ LX Processors Data Book -...
Page 9 Table 7-6. AMD Geode LX 600@0.7W Processor DC Currents ......603 Table 7-7.
Page 10 AMD 3DNow!™ Technology Instruction Set ........
Page 11: 1.0Overview
Overview General Description AMD Geode™ LX processors are integrated x86 proces- sors specifically designed to power embedded devices for entertainment, education, and business. Serving the needs of consumers and business professionals alike, it’s an excellent solution for embedded applications, such as thin clients, interactive set-top boxes, single board computers, and mobile computing devices.
Page 12: Features
*The AMD Geode LX 900@1.5W processor operates at 600 MHz, the AMD Geode LX 800@0.9W processor operates at 500 MHz, the AMD Geode LX 700@0.8W processor operates at 433 MHz and the AMD Geode LX 600@.07W processor operates at 366 MHz. Model numbers reflect performance as described here: http://www.amd.com/connectivitysolutions/geodelxbenchmark.
Page 13 Integrated Dot Clock PLL with up to 350 MHz clock ■ Integrated 3x8-bit DAC with up to 350 MHz sampling ■ Integrated x86 core PLL ■ Memory PLL AMD Geode™ LX Processors Data Book 33234H GeodeLink™ PCI Bridge ■ PCI 2.2 compliant ■ 3.3V signaling and 3.3V I/Os ■...
Page 14 33234H Overview AMD Geode™ LX Processors Data Book...
Page 15: 2.0Architecture Overview
Internet content available while the intelli- gent integration of several other functions, including graph- ics, makes the AMD Geode™ LX processor a true system- level multimedia solution. The AMD Geode LX processor can be divided into major functional blocks (as shown in Figure 1-1 on page 11): •...
Page 16: Geodelink™ Control Processor
SDRAM, are supported with up to 512 MB in each bank. Four banks means that one or two DIMM or SODIMM mod- ules can be used in a AMD Geode LX processor system. Some memory configurations have additional restrictions on maximum device quantity.
Page 17: Graphics Processor
Architecture Overview Graphics Processor The Graphics Processor is based on the graphics proces- sor used in the AMD Geode GX processor with several fea- tures added to enhance performance and functionality. Like its predecessor, the AMD Geode LX processor’s Graphics...
Page 18: Display Controller
The Display Controller consists of a memory retrieval sys- tem for rasterized graphics data, a VGA, and a back-end fil- ter. The AMD Geode LX processor’s Display Controller corresponds to the Display Controller function found in the AMD Geode GX processor with additional hardware for graphics filter functions.
Page 19: Security Block
Architecture Overview 2.10 Security Block The AMD Geode LX processor has an on-chip AES 128-bit crypto acceleration block capable of 44 Mbps throughput on either encryption or decryption at a processor speed of 500 MHz. The AES block runs asynchronously to the pro- cessor core and is DMA based.
Page 20 33234H Architecture Overview AMD Geode™ LX Processors Data Book...
Page 21: 3.0Signal Definitions
Signal Definitions This chapter defines the signals and describes the external interface of the AMD Geode™ LX processor. Figure 3-1 shows the pins organized by their functional groupings. Where signals are multiplexed, the default signal name is listed first and is separated by a plus sign (+).
Page 22: Table 3-1. Video Signal Definitions Per Mode
B[7:0] (Note 2) VOP[7:0] (O) DOTCLK (O) VOPCLK (O) VOP_HSYNC (O) VOP_HSYNC (O) VSYNC (O) VOP_VSYNC (O) DISPEN (O) VOP_BLANK (O) VDDEN (O) VIP_HSYNC (I) LDEMOD (O) VIP_VSYNC (I) VID[7:0] VID[7:0] VIPCLK VIPCLK VIPSYNC VIPSYNC AMD Geode™ LX Processors Data Book...
Page 23: Buffer Types
24/Q5 24/Q7 DDRCLK Wire AMD Geode™ LX Processors Data Book PU/PD: Indicates if an internal, programmable pull-up or pull-down resistor may be present. Current High/Low (mA): This column gives the current source/sink capacities when the voltage at the pin is high, and low.
Page 24: Bootstrap Options
33234H Bootstrap Options The bootstrap options shown in Table 3-3 are supported in the AMD Geode LX processor for configuring the system. Table 3-3. Bootstrap Options Pins Description IRQ13 0: Normal boot operation, TAP reset active during PCI reset 1: Debug stall of CPU after CPU...
Page 25: Figure 3-2. Bgu481 Ball Assignment Diagram
Note: Signal names have been abbreviated in this figure due to space constraints. = GND Ball = PWR Ball = Strap Option Ball = Multiplexed Ball Figure 3-2. BGU481 Ball Assignment Diagram AMD Geode™ LX Processors Data Book DQ26 DQ31 V DQ32 DQ37 V DQM4 DQ39 DQ27 TLA1...
Page 26: Table 3-5. Ball Assignments - Sorted By Ball Number
(Note 1) (PD) Type CORE CORE MA10 SDCLK5P DDRCLK SDCLK5N DDRCLK SDCLK4P DDRCLK SDCLK4N DDRCLK RAS1# CS3# DQ48 DQ11 CKE0 CAS0# CAS1# DQ15 DQ14 DQ10 CKE1 CS1# CS2# MA13 DQ49 DQ13 DQM1 DQ52 DQ53 AMD Geode™ LX Processors Data Book...
Page 27 SDCLK2N DDRCLK DQ60 DQM0 DQS0 SDCLK0P DDRCLK SDCLK2P DDRCLK DQ61 DQ57 DQ56 CORE CORE CORE CORE AMD Geode™ LX Processors Data Book Ball Signal Name Type Buffer (Note 1) (PD) Type DQM7 DQS7 MVREF CORE CORE CORE CORE DQ62 CORE...
Page 28 AJ14 AJ15 VID0 I/O (PD) 24/Q7 AJ16 AJ17 24/Q7 AJ18 AJ19 AJ20 AJ21 AJ22 CBE0# AJ23 AJ24 AD15 AJ25 STOP# AJ26 AJ27 AJ28 AD16 AJ29 AJ30 AD19 AJ31 AD21 DRGB9 O (PD) 24/Q5 VOP14 AMD Geode™ LX Processors Data Book...
Page 29 I/O (PD) 24/Q7 AK14 AK15 VID1 I/O (PD) 24/Q7 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AD10 AMD Geode™ LX Processors Data Book Ball Signal Name Type Buffer (Note 1) (PD) Type AK24 AK25 DEVSEL# AK26 TRDY# AK27 AK28 AD17...
Page 30: Table 3-6. Ball Assignments - Sorted Alphabetically By Signal Name
DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DRGB0 DRGB1 DRGB2 DRGB3 DRGB4 DRGB5 DRGB6 AMD Geode™ LX Processors Data Book...
Page 31 GNT0# AA28 GNT1# AB30 GNT2# AC30 GREEN HSYNC INTA# AD28 IRDY# AH25 IRQ13 AB29 LDEMOD MA10 AMD Geode™ LX Processors Data Book Signal Name Ball No. MA11 MA12 MA13 MLPF MSGSTART AH11 MSGSTOP AJ11 MVREF AJ27 AL18 AJ17 RAS0# RAS1#...
Page 32 T16, A24, T17, T18, T19, T28, T29, T30, T31, U13, U14, U15, A27, U16, U17, U18, U19, V15, V16, V17, W15, W16, W17, W28, Y4, Y29 Signal Definitions Signal Name Ball No. VSYNC WE0# WE1# AMD Geode™ LX Processors Data Book...
Page 33: Signal Descriptions
66 MHz. 48 MHz Dot Clock Reference. Input clock for DOTCLK PLL. 0-66 Mb/s Interrupt. Interrupt from the AMD Geode LX proces- sor to the CS5536 companion device (open drain). 0-66 Mb/s Interrupt Request Level 13. When a floating point error occurs, the AMD Geode LX processor asserts IRQ13.
Page 34 Video PLL Analog Ground. Connect to ground. Analog Core PLL Low Pass Filter. 220 pF to CAV Analog GLIU PLL Low Pass Filter. 220 pF to MAV Analog Video PLL Low Pass Filter. 220 pF to VAV Signal Definitions AMD Geode™ LX Processors Data Book...
Page 35 DQS[7:0] N31, J29, B23, C19, A10, C6, H3, M2 AMD Geode™ LX Processors Data Book Description up to 200 MHz SDRAM Clock Differential Pairs. The SDRAM devices sample all the control, address, and data based on these clocks. All clocks are dif- ferential clock outputs.
Page 36 GLCP module to be edge sensitive or level sensitive 0-400 Mb/s Test Debug Output. The AMD Geode LX pro- cessor can output internal clocks on TDBGO. The selects for TDBGO are MSR programmable via the GLCP module. The internal clock can be selected from any clock domain and may be divided down by 2 or 3 before output.
Page 37 CBE[3:0]# AH31, AH27, AL26, AJ22 AJ27 AMD Geode™ LX Processors Data Book Description 33-66 Mb/s Multiplexed Address and Data. Addresses and data are multiplexed together on the same pins. A bus transaction consists of an address phase in the cycle in which FRAME# is asserted fol- lowed by one or more data phases.
Page 38 Description 0-1 Mb/s PCI Reset. RESET# aborts all operations in progress and places the AMD Geode LX proces- sor into a reset state. RESET# forces the CPU and peripheral functions to begin executing at a known state. All data in the on-chip cache is invalidated upon a reset.
Page 39 AA29 GNT[2:0]# AC30, AB30, AA28 (Strap) AMD Geode™ LX Processors Data Book Description 33-66 Mb/s Device Select. DEVSEL# indicates that the driv- ing device has decoded its address as the target of the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected.
Page 40 Video Output Port Data. VOP output data. 0-75 MHz Video Output Port Clock. 0-75 Mb/s Video Output Port Blank. 0-75 Mb/s Video Output Port Horizontal Sync. 0-75 Mb/s Video Output Port Vertical Sync. Signal Definitions voltage is applied to the AMD Geode™ LX Processors Data Book...
Page 41 AK15, AJ15 VIPSYNC AL14 (PD) VIP_HSYNC VIP_VSYNC AMD Geode™ LX Processors Data Book Description 0-350 Mb/s Horizontal Sync. Horizontal Sync establishes (5vt) the line rate and horizontal retrace interval for an attached CRT. The polarity is programmable (See Section 6.8.3.2 on page 422, VP Memory Offset 008h[8]).
Page 42 For additional electrical details on pins, refer to Section 7.0 "Electrical Specifications" on page 597. Description Core Power Connection (Total of 32). I/O Power Connection (Total of 30) Memory Power Connection (Total of 33). Ground Connection (Total of 128). AMD Geode™ LX Processors Data Book Signal Definitions...
Page 43: Table 3-7. Signal Behavior During And After Reset
Video PD during reset. VSYNC Video Driven low during RESET# low HSYNC DISPEN DOTCLK DRGB[23:0] LDEMOD VDDEN CKE[1:0]# AMD Geode™ LX Processors Data Book 33234H Signal Name Type Behavior VID[7:0] (PD) Video Inputs during RESET# low VIPCLK System TDBGI Debug...
Page 44 33234H Signal Definitions AMD Geode™ LX Processors Data Book...
Page 45: 4.0Geodelink™ Interface Unit
ECX register. The RDMSR and WRMSR instruc- tions are privileged instructions. Table 4-1 shows the MSR port address to access the mod- ules within the AMD Geode LX processor with the CPU Core as the source module. Table 4-1. MSR Addressing...
Page 46: Figure 4-1. Geodelink™ Architecture
The internal architecture of the companion device uses the same GeodeLink architecture with one GLIU being in that device. Hence, in a AMD Geode LX proces- sor/CS5536 system there are a total of three GLIUs: two in the processor and one in the companion device. Therefore...
Page 47: Table 4-2. Msr Mapping
GLIU in the chain. The CPU Core accessing 2.1.0.0.0.0 also causes a reflective address error. To access modules in the AMD Geode companion device, the port address must go through the GLPCI (PCI control- ler) in the processor and through the GLPCI in the compan- ion device.
Page 48: Table 4-3. Gliu Memory Descriptor Address Hit And Routing Description
Swiss cheese feature implies that the descriptor is used to “poke holes” in memory. Note: Only one P2D can hit at a time for a given port. If the P2D descriptors are overlapping, the results are undefined. AMD Geode™ LX Processors Data Book...
Page 49: Table 4-4. Gliu I/O Descriptor Address Hit And Routing Description
If the above matches, then the descriptor has a hit condition and routes the received address to the programmed des- tination ID, PDID1 field of the descriptor register bits [63:61]. DEVICE_ADDR = request address AMD Geode™ LX Processors Data Book 33234H for legacy address mapping. The Swiss cheese feature implies that the descriptor is used to “poke holes”...
Page 50: Gliu Register Descriptions
Configuration Dependent Boot Strap Dependent 10000000_00000000h 00000000_00000000h 00000000_00000000h GLIU0: 20291830_010C1086h GLIU1: 20311030_0100400Ah 00000000_00000000h 00000000_00000000h AMD Geode™ LX Processors Data Book Reference Page 55 Page 55 Page 56 Page 57 Page 59 Page 60 Reference Page 60 Page 61 Page 62...
Page 51: Table 4-7. Gliu Statistic And Comparator Msrs Summary
Descriptor Statistic Counter GLIU1: 400000ACh (STATISTIC_CNT[3]) GLIU0: 100000ADh Descriptor Statistic Mask GLIU1: 400000ADh (STATISTIC_MASK[3]) GLIU0: 100000AEh Descriptor Statistic Action GLIU1: 400000AEh (STATISTIC_ACTION[3]) AMD Geode™ LX Processors Data Book 33234H Reset Value Reference GLIU0: Page 67 00000000_00000010h GLIU1: 00000000_00000100h Configuration Dependent Page 68...
Page 52 Page 78 00000000_00000000h Page 79 00001FFF_FFFFFFFFh Page 76 0000000F_FFFFFFFFh Page 77 00000000_00000000h Page 78 00000000_00000000h Page 79 00000000_00000000h Page 79 0000000F_FFFFFFFFh Page 77 00000000_00000000h Page 78 00000000_00000000h Page 79 00001FFF_FFFFFFFFh Page 76 0000000F_FFFFFFFFh Page 77 AMD Geode™ LX Processors Data Book...
Page 53: Table 4-8. Gliu P2D Descriptor Msrs Summary
4000002Fh- P2D Reserved Descriptor 4000003Fh (P2D_RSVD) Table 4-9. GLIU Reserved MSRs Summary MSR Address Type Register GLIU0: 10000006h- Reserved for future use by AMD. 1000000Fh GLIU1: 40000006h- 4000000Fh GLIU0: 10000040h- Reserved for future use by AMD. 1000004Fh GLIU1: 40000040h- 4000004Fh GLIU0: 10000050h- Reserved for future use by AMD.
Page 54: Table 4-10. Gliu Iod Descriptor Msrs Summary
IOD Base Mask Descriptors (IOD_BM) 400000E2h 400000E3h- IOD Swiss Cheese Descriptors (IOD_SC) 400000E6h 400000E7h- IOD Reserved Descriptors 400000FFh GLIU Register Descriptions Reset Value Reference 000000FF_FFF00000h Page 86 00000000_00000000h Page 87 000000FF_FFF00000h Page 86 00000000_00000000h Page 87 AMD Geode™ LX Processors Data Book...
Page 55 Description 63:24 RSVD Reserved. 23:8 DEV_ID Device ID. Identifies device (0014h). REV_ID Revision ID. Identifies device revision. See AMD Geode™ LX Processors Specification Update document for value 4.2.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG) MSR Address GLIU0: 10002001h GLIU1: 40002001h Type...
Page 56 SMI Mask1. Write 0 to enable SFLAG1 (bit 33) and to allow a Statistic Counter 0 (GLIU0 MSR 100000A0h, GLIU1 MSR 400000A0h) event to generate an SMI. SMASK0 SMI Mask0. Unexpected Type (HW Emulation). _MSR_SMI Register Map RSVD RSVD _MSR_SMI Bit Descriptions GLIU Register Descriptions AMD Geode™ LX Processors Data Book...
Page 57 Request Comparator 1 (RQ_COMPARE_VAL1, GLIU0 MSR 100000C2h, GLIU1 MSR 400000C2h) event. Write 1 to clear; writing 0 has no effect. EMASK8 (bit 8) must be low to generate ERR and set flag. AMD Geode™ LX Processors Data Book _MSR_ERROR Register Map _MSR_ERROR Bit Descriptions...
Page 58 Request Comparator Error Mask 2. Write 0 to enable EFLAG9 (bit 41) and to allow a Request Comparator 2 (RQ_COMPARE_VAL2, GLIU0 MSR 100000C4h, GLIU1 MSR 400000C4h) event to generate an ERR. _MSR_ERROR Bit Descriptions (Continued) GLIU Register Descriptions AMD Geode™ LX Processors Data Book...
Page 59 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 AMD Geode™ LX Processors Data Book _MSR_ERROR Bit Descriptions (Continued)
Page 60 GLD Diagnostic MSR (GLD_MSR_DIAG) MSR Address GLIU0: 10002005h GLIU1: 40002005h Type Reset Value 00000000_00000000h This register is reserved for internal use by AMD and should not be written to. 4.2.2 GLIU Specific Registers 4.2.2.1 Coherency (COH) MSR Address GLIU0: 10000080h...
Page 61 Port Active Enable for Port 2. (GLIU0 = Interface to GLIU1; GLIU1 = VP.) See bits [15:14] for decode. PAE1 Port Active Enable for Port 1. (GLIU0 = GLMC; GLIU1 = Interface to GLIU0.) See bits [15:14] for decode. AMD Geode™ LX Processors Data Book PAE Register Map RSVD PAE0 PAE7...
Page 62 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 RSVD ARB Register Map RSVD RSVD ARB Bit Descriptions ASMI Register Map RSVD AMD Geode™ LX Processors Data Book GLIU Register Descriptions...
Page 63 AERR is a condensed version of the port ERR signals. The MASK bits can be used to prevent a device from issuing an AERR. If the MASK = 1, the device’s AERR is disabled. AMD Geode™ LX Processors Data Book ASMI Bit Descriptions...
Page 64 Asynchronous Error for Port 0 (Read Only). (GLIU0 = GLIU; GLIU1 = GLIU.) If 1, indi- (RO) cates that an AERR was generated by Port 0. Cleared by source. AERR Register Map RSVD AERR Bit Descriptions AMD Geode™ LX Processors Data Book GLIU Register Descriptions...
Page 65 Number of P2D_RO Descriptors. 17:12 NP2D_R Number of P2D_R Descriptors. 11:6 NP2D_BMO Number of P2D_BMO Descriptors. NP2D_BM Number of P2D_BM Descriptors. AMD Geode™ LX Processors Data Book PHY_CAP Register Map NPORTS NCOH NIOD_SC NP2D_RO NP2D_R PHY_CAP Bit Descriptions 33234H NIOD_BM...
Page 66 Number of Outstanding Responses on Port 1. (GLIU0 = GLMC; GLIU1 = Interface to GLIU0.) NOOUT_RESP0 Number of Outstanding Responses on Port 0. (GLIU0 = GLIU; GLIU1 = GLIU.) NOUT_RESP Register Map NOUT_RESP6 NOUT_RESP5 NOUT_RESP2 NOUT_RESP1 NOUT_RESP Bit Descriptions GLIU Register Descriptions NOUT_RESP4 NOUT_RESP9 AMD Geode™ LX Processors Data Book...
Page 67 Port 7 Slave Only. (GLIU0 = Not Used; GLIU1 = Not Used.) If high, indicates that Port 7 is a slave port. If low, Port 7 is a master/slave port. AMD Geode™ LX Processors Data Book NOUT_WDATA Register Map NOUT_WDATA6...
Page 68 110: Port 6 (GLIU0 = Not Used; GLIU1 = SB.) 111: Port 7 (GLIU0 = Not Used; GLIU1 = Not Used.) WHO AM I Register Map RSVD RSVD WHO AM I Bit Descriptions GLIU Register Descriptions DSID AMD Geode™ LX Processors Data Book...
Page 69 Write 1 to disable slave transactions to Port 1. SLAVE_DIS0 Slave Transactions Disable for Port 0. (GLIU0 = GLIU; GLIU1 = GLIU.) Write 1 to dis- able slave transactions to Port 0. AMD Geode™ LX Processors Data Book GLIU_SLV Register Map RSVD GLIU_SLV Bit Descriptions...
Page 70 GLIU is retreating a priority above the THRESH priority. THRESH Priority Threshold. See THROT_EN description. Priority threshold value must be 4 or less. 0: Disable. 1: Enable. ARB2 Register Map RSVD RSVD ARB2 Bit Descriptions AMD Geode™ LX Processors Data Book GLIU Register Descriptions THRESH...
Page 71 Counter Load Value. The value loaded here is used as the initial Statistics Counter value when a LOAD action occurs or is commanded. 31:0 Counter Value. These bits provide the current counter value when read. AMD Geode™ LX Processors Data Book Descriptor Statistic Counter (STATISTIC_CNT[2]) MSR Address Type...
Page 72 Type Reset Value Descriptor Statistic Mask (STATISTIC_MASK[3]) MSR Address Type Reset Value STATISTIC_MASK[0:3] Register Map IOD_MASK P2D MASK STATISTIC_MASK[0:3] Bit Descriptions GLIU Register Descriptions GLIU0: 100000A9h GLIU1: 400000A9h 00000000_00000000h GLIU0: 100000ADh GLIU1: 400000ADh 00000000_00000000h AMD Geode™ LX Processors Data Book...
Page 73 HIT_AERR Assert AERR on Descirptor Hit. The descriptor hits are ANDed with the masks and then all ORed together. 0: Disable. 1: Enable AMD Geode™ LX Processors Data Book Descriptor Statistic Action (STATISTIC_ACTION[2]) MSR Address Type Reset Value Descriptor Statistic Action (STATISTIC_ACTION[3])
Page 74 Request Compare Value (RQ_COMPARE_VAL[2]) MSR Address Type Reset Value Request Compare Value (RQ_COMPARE_VAL[3]) MSR Address Type Reset Value RQ_COMPARE_VAL[0:3] Register RQ_VAL RQ_VAL GLIU Register Descriptions GLIU0: 100000C4h GLIU1: 400000C4h 001FFFFF_FFFFFFFFh GLIU0: 100000C6h GLIU1: 400000C6h 001FFFFF_FFFFFFFFh AMD Geode™ LX Processors Data Book...
Page 75 Reserved. 52:0 RQ_MASK Request Packet Mask. This field is bit-wise logically ANDed with the incoming request packet before it is compared to the RQ_COMPVAL. AMD Geode™ LX Processors Data Book 33234H Request Compare Mask (RQ_COMPARE_MASK[2]) MSR Address GLIU0: 100000C5h GLIU1: 400000C5h...
Page 76 Data Compare Value Low (DA_COMPARE_VAL_LO[2]) MSR Address Type Reset Value Data Compare Value Low (DA_COMPARE_VAL_LO[3]) MSR Address Type Reset Value DA_COMPARE_VAL_LO[0:3] Register DALO_VAL GLIU Register Descriptions GLIU0: 100000D8h GLIU1: 400000D8h 00001FFF_FFFFFFFFh GLIU0: 100000DCh GLIU1: 400000DCh 00001FFF_FFFFFFFFh DALO_VAL AMD Geode™ LX Processors Data Book...
Page 77 ‘hit’. The “HI” and “LO” portions of the incoming data, the compare value, and the compare mask, are assembled into complete bit patterns before these operations occur. AMD Geode™ LX Processors Data Book Data Compare Value High (DA_COMPARE_VAL_HI[2]) MSR Address...
Page 78 Data Compare Mask Low (DA_COMPARE_MASK_LO[2]) MSR Address GLIU0: 100000DAh GLIU1: 400000DAh Type Reset Value 00000000_00000000h Data Compare Mask Low (DA_COMPARE_MASK_LO[3]) MSR Address GLIU0: 100000DEh GLIU1: 400000DEh Type Reset Value 00000000_00000000h DALO_MASK DALO_MASK AMD Geode™ LX Processors Data Book GLIU Register Descriptions...
Page 79 DA_COMPVAL.The “HI” and “LO” portions of the incoming data. the compare value, and the compare mask, are assembled into complete bit pat- terns before these operations occur. AMD Geode™ LX Processors Data Book Data Compare Mask High (DA_COMPARE_MASK_HI[2])
Page 80 Physical Memory Address Mask. These bits are used to mask address bits [31:12] for the purposes of this ‘hit’ detection. GLIU1 MSR Address 40000020h-40000029h Type Reset Value P2D_BM Register Map RSVD PMASK P2D_BM Bit Descriptions GLIU Register Descriptions P2D_BM[9:0] 000000FF_FFF00000h PBASE AMD Geode™ LX Processors Data Book...
Page 81 “hit’ is declared, depending on the setting of the Bizzaro flag comparator. 19:0 PMASK Physical Memory Address Mask. These bits are used to mask address bits [31:12] for the purposes of this ‘hit’ detection. AMD Geode™ LX Processors Data Book P2D_BMO Register Map POFFSET PMASK P2D_BMO Bit Descriptions...
Page 82 Hence, a hit occurs if the physical address [31:12] >= PMIN and <= PMAX. GLIU1 P2D_R[3:0] MSR Address 4000002Ah-4000002Dh Type Reset Value 00000000_000FFFFFh P2D_R Register Map RSVD PMIN P2D_R Bit Descriptions AMD Geode™ LX Processors Data Book GLIU Register Descriptions PMAX...
Page 83 Physical Memory Address Min. These bits form the value denoting the lower (starting) address of the physical memory, which is compared to determine a hit. Hence, a hit occurs if the physical address [31:12] >= PMIN and <= PMAX. AMD Geode™ LX Processors Data Book P2D_RO Register Map OFFSET...
Page 84 [31:18] are equal to PBASE. Bits [17:14] of the physical address are used to choose the ith 16K region of WEN/REN for a hit. GLIU1 P2D_SC[0] MSR Address 4000002Eh Type Reset Value 00000000_00000000h P2D_SC Register Map P2D_SC Bit Descriptions GLIU Register Descriptions PSCBASE AMD Geode™ LX Processors Data Book...
Page 85 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Name Description 63:0 SPARE_MSR Spare MSR. AMD Geode™ LX Processors Data Book SPARE_MSR[x] Register Map SPARE_MSR SPARE_MSR SPARE_MSR[x] Bit Descriptions 33234H...
Page 86 Physical I/O Address Mask. These bits are used to mask address bits [31:12] for the purposes of this ‘hit’ detection. GLIU1 MSR Address Type Reset Value IOD_BM[x] Register Map RSVD IMASK IOD_BM[x] Bit Descriptions GLIU Register Descriptions IOD_BM[0:3] 400000E0h-400000E2h 000000FF_FFF00000h IBASE AMD Geode™ LX Processors Data Book...
Page 87 [31:18] are equal to the PBASE field of descriptor register bits [13:0]. RSVD Reserved. Write as read. AMD Geode™ LX Processors Data Book GLIU1 MSR Address Type Reset Value...
Page 88 33234H GLIU Register Descriptions AMD Geode™ LX Processors Data Book...
Page 89: 5.0Cpu Core
CPU Core This section describes the internal operations of the AMD Geode™ LX processor’s CPU Core from a program- mer’s point of view. It includes a description of the tradi- tional “core” processing and FPU operations. The integrated function registers are described in the next chapter.
Page 90: Instruction Set Overview
Control, System Address, Debug, Configuration, and Test registers. All accesses to the these registers use special CPU instructions. Both of these register sets are discussed in detail in the subsections that follow. AMD Geode™ LX Processors Data Book CPU Core...
Page 91: Application Register Set
General Purpose Registers Segment (Selector) Registers Instruction Pointer and EFLAGS Registers AMD Geode™ LX Processors Data Book that contain the base address for each segment, as well as other memory addressing information. The Instruction Pointer register points to the next instruc- tion that the processor will execute.
Page 92: Table 5-3. Segment Register Selection Rules
(for example JMP and CALL). Implied (Default) Segment-Override Segment Prefix None None None None CS, ES, FS, GS, SS CS, DS, ES, FS, GS AMD Geode™ LX Processors Data Book CPU Core...
Page 93: Table 5-4. Eflags Register
Carry Flag. Set when a carry out of (addition) or borrow into (subtraction) the most significant bit of the result occurs; cleared otherwise. AMD Geode™ LX Processors Data Book lower 16 bits of this register are used when executing 8086 or 80286 code.
Page 94: System Register Set
Registers FPUn Floating Point Unit Shadow Registers Descriptor GDTR GDT Register Table IDTR IDT Register Registers LDTR LDT Register Task Register Task Register Performance PCRn Performance Registers Control Registers AMD Geode™ LX Processors Data Book CPU Core Width (Bits)
Page 95: Table 5-6. Control Registers Map
CR0 Register Control Register 0 (R/W) RSVD AMD Geode™ LX Processors Data Book The CD bit (Cache Disable, bit 30) in CR0 globally controls the operating mode of the L1 and L2 caches. LCD and LWT, Local Cache Disable and Local Write-through bits in the Translation Lookaside Buffer, control the mode on a page-by-page basis.
Page 96: Table 5-7. Cr4 Bit Descriptions
After changing the state of PG, software must execute an unconditional branch instruction (e.g., JMP, CALL) to have the change take effect. Table 5-7. CR4 Bit Descriptions Table 5-8. CR3 Bit Descriptions Table 5-9. CR2 Bit Descriptions Table 5-10. CR0 Bit Descriptions CPU Core AMD Geode™ LX Processors Data Book...
Page 97 8086-style CPU. Note 1. For effects of various combinations of the TS, EM, and MP bits, see Table 5-11 on page 98. AMD Geode™ LX Processors Data Book Normal Cache operation, coherency maintained. Read hits access the cache,...
Page 98: Table 5-11. Effects Of Various Combinations Of Em, Ts, And Mp Bits
Table 5-11. Effects of Various Combinations of EM, TS, and MP Bits CR0[3:1] Instruction Type WAIT Execute Execute Execute Fault 7 Execute Execute Execute Fault 7 AMD Geode™ LX Processors Data Book CPU Core Execute Execute Fault 7 Fault 7 Fault 7 Fault 7 Fault 7 Fault 7...
Page 99: Cpu Core Register Descriptions
00001108h IF Test Address MSR (IF_TEST_ADDR_MSR) 00001109h IF Test Data MSR (IF_TEST_DATA_MSR) AMD Geode™ LX Processors Data Book 33234H meaning a RDMSR/WRMSR instruction attempting to use the address generates a General Protection Fault. The registers associated with the CPU Core are the Stan- dard GeodeLink™...
Page 100 Page 131 xxxxxxxx_xxxxxxxxh Page 131 xxxxxxxx_xxxxxxxxh Page 131 xxxxxxxx_xxxxxxxxh Page 131 xxxxxxxx_xxxxxxxxh Page 131 00000000_00000000h Page 132 00000000_00000000h Page 133 xxxxxxxx_xxxxxxxxh Page 134 xxxxxxxx_xxxxxxxxh Page 134 xxxxxxxx_xxxxxxxxh Page 134 xxxxxxxx_xxxxxxxxh Page 134 xxxxxxxx_xxxxxxxxh Page 134 AMD Geode™ LX Processors Data Book...
Page 101 00001371h Floating Point Environment Instruction Pointer (FPENV_IP_MSR) 00001372h Floating Point Environment Data Segment (FPENV_DS_MSR) 00001373h Floating Point Environment Data Pointer (FPENV_DP_MSR) AMD Geode™ LX Processors Data Book 33234H Reset Value Reference xxxxxxxx_xxxxxxxxh Page 134 xxxxxxxx_xxxxxxxxh Page 134 xxxxxxxx_xxxxxxxxh Page 134...
Page 102 Page 148 00000000_00000002h Page 149 00000000_60000010h Page 149 00000000_00000000h Page 150 00000000_00000000h Page 152 xxxxxxxx_xxxxxxxxh Page 152 00000000_00000000h Page 153 00000000_00000000h Page 154 xxxxxxxx_xxxxxxxxh Page 154 00000000_xxxxxxxxh Page 154 00000000_0000000xh Page 155 00000000_00000000h Page 156 AMD Geode™ LX Processors Data Book...
Page 103 00001810h Region Configuration Range 0 MSR (RCONF0_MSR) 00001811h Region Configuration Range 1 MSR (RCONF1_MSR) 00001812h Region Configuration Range 2 MSR (RCONF2_MSR) AMD Geode™ LX Processors Data Book 33234H Reset Value Reference xxxxxxxx_xxxxxxxxh Page 157 xxxxxxxx_xxxxxxxxh Page 157 xxxxxxxx_xxxxxxxxh Page 157...
Page 104 Page 174 00000000_xxxxxxxxh Page 175 00000000_00000000h Page 175 00000000_00000000h Page 176 00000000_00000000h Page 177 00000000_00000000h Page 178 00000000_00000000h Page 178 00000000_00000000h Page 179 00000000_00000000h Page 180 00000000_00000000h Page 182 00000000_00000000h Page 182 00000000_00000111h Page 183 AMD Geode™ LX Processors Data Book...
Page 105 (MSS_ARRAY_CTL0_MSR) 00001982h Memory Subsystem Array Control 1 MSR (MSS_ARRAY_CTL1_MSR) 00001983h Memory Subsystem Array Control 2 MSR (MSS_ARRAY_CTL2_MSR) 00001A00h FPU Modes MSR (FP_MODE_MSR) AMD Geode™ LX Processors Data Book 33234H Reset Value Reference 00000000_00000000h Page 184 00000000_00000000h Page 185 00000000_00000000h Page 185...
Page 106 Page 206 xxxxxxxx_xxxxxxxxh Page 205 00000000_0000xxxxh Page 206 xxxxxxxx_xxxxxxxxh Page 205 00000000_0000xxxxh Page 206 xxxxxxxx_xxxxxxxxh Page 205 00000000_0000xxxxh Page 206 xxxxxxxx_xxxxxxxxh Page 205 00000000_0000xxxxh Page 206 xxxxxxxx_xxxxxxxxh Page 205 00000000_0000xxxxh Page 206 xxxxxxxx_xxxxxxxxh Page 207 AMD Geode™ LX Processors Data Book...
Page 107 CPU Marketing Name 6 (CPUIDF_MSR) 00003010h L1 TLB Information (CPUID10_MSR) 00003011h L1 Cache Information (CPUID11_MSR) 00003012h L2 TLB Information (CPUID12_MSR) 00003013h L2 Cache Information (CPUID13_MSR) AMD Geode™ LX Processors Data Book 33234H Reset Value Reference 68747541_00000001h Page 207 69746E65_444D4163h Page 207 00000400_000005A2h...
Page 108 63:24 RSVD Reserved. Reads as 0. 23:8 DEV_ID Device ID. Identifies device (0864h). REV_ID Revision ID. Identifies device revision. See AMD Geode™ LX Processors Specification Update document for value. 5.5.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG) MSR Address 00002001h Type Reset Value...
Page 109 This register is not used in the CPU Core module. 5.5.1.6 GLD Diagnostic Bus Control MSR (GLD_MSR_DIAG) MSR Address 00002005h Type Reset Value 00000000_00000000h This register is reserved for internal use by AMD and should not be written to. AMD Geode™ LX Processors Data Book 33234H...
Page 110 Event Counter 0 Select MSR (MSR 00000186h). TSC_MSR Register Map TSC (High DWORD) TSC (Low DWORD) TSC_MSR Bit Descriptions PERF_CNT0_MSR Register Map RSVD PERF_CNT0 (Low DWORD) PERF_CNT0_MSR Bit Descriptions CPU Core Register Descriptions PERF_CNT0 (High Byte) AMD Geode™ LX Processors Data Book...
Page 111 Performance Event Counter 1. This register is a 40-bit event counter used to count events or conditions inside the CPU Core. This counter is controlled by Performance Event Counter 1 Select MSR (MSR 00000187h). AMD Geode™ LX Processors Data Book PERF_CNT1_MSR Register Map RSVD...
Page 112 Code Segment Selector. (Default = 0) Descriptor Table Indicator. (Default = 0) RPL (RO) Requestor Privilege Level (Read Only). (Default = 0) SYS_CS_MSR Register Map RSVD SYS_CS_MSR Bit Descriptions CPU Core Register Descriptions CS_SEL AMD Geode™ LX Processors Data Book...
Page 113 Name Description 63:32 RSVD Reserved. 31:0 Enter Instruction Pointer. Offset into the most privileged code segment. (Default = 0) AMD Geode™ LX Processors Data Book SYS_SP_MSR Register Map RSVD SYS_SP_MSR Bit Descriptions SYS_IP_MSR Register Map RSVD SYS_IP_MSR Bit Descriptions 33234H...
Page 114 Performance Event Counter 1 Event Select Value. See individual module chapters for performance event selections. PERF_SEL0_MSR Register Map RSVD RSVD PC0_UMASK PERF_SEL0_MSR Bit Descriptions PERF_SEL1_MSR Register Map RSVD PC1_UMASK PERF_SEL1_MSR Bit Descriptions CPU Core Register Descriptions PC0_EVENT PC1_EVENT AMD Geode™ LX Processors Data Book...
Page 115 32 = Way 0, bit 33 = Way 1, bit 34 = Way 2, and bit 35 = Way 3. 0: Enable Way. (Default) 1: Disable Way. 31:29 RSVD Reserved. AMD Geode™ LX Processors Data Book IF_CONFIG_MSR Register Map RSVD IF_CONFIG_MSR Bit Descriptions 33234H RSVD...
Page 116 (bit 0 = 1), then CC_L0 has no effect. Disabling the COF cache and return stack during DMM may reduce performance but make debug easier. CC_L1 must be disabled (bit 0 = 0) to enable power saving. CPU Core Register Descriptions AMD Geode™ LX Processors Data Book...
Page 117 Level-1 COF Cache. 0: Disable. 1: Enable. (Default) Note: AMD Geode™ LX Processors Data Book Enabling strong predictions may improve performance. Enabling the return stack increases performance unless CC_L1 is enabled (bit 0 = 1), then the return stack has no effect.
Page 118 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD Name Description 63:13 RSVD Reserved. IF_INVALIDATE_MSR Register Map RSVD RSVD IF_INVALIDATE_MSR Bit Descriptions IF_TEST_ADDR_MSR Register Map RSVD IF_TEST_ADDR_MSR Bit Descriptions CPU Core Register Descriptions RS CC BLOCK INDEX AMD Geode™ LX Processors Data Book...
Page 119 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 IF_TEST_DATA_MSR Bit Descriptions for Target RAMs Name Description 63:32 RSVD Reserved. 31:0 COF Target. AMD Geode™ LX Processors Data Book 33234H RSVD...
Page 120 Next Entry. Indicates that entry is the next entry to be written. Exactly one of the four entries should have this bit set. RSVD RSVD STRENGTH TYPE RSVD RSVD CPU Core Register Descriptions RSVD RSVD TYPE RSVD AMD Geode™ LX Processors Data Book...
Page 121 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 IF_TEST_DATA_MSR Bit Descriptions for Return Stack Addresses Name Description 63:32 RSVD Reserved. 31:0 ADDR[31:0] Address Bits [31:0]. Linear address to which a Return instruction should return. AMD Geode™ LX Processors Data Book 33234H RSVD ADDR[31:0] RSVD TARGET[31:0] RSVD ADDR[31:0]...
Page 122 63:5 RSVD Reserved. SEQCOUNT Sequential Count. Number of sequential instructions executed since the last change of flow. RSVD ID_SPEC_VLD IF_SPEC_VLD[7:0] IF_SEQCOUNT_MSR Register Map RSVD RSVD IF_SEQCOUNT_MSR Bit Descriptions CPU Core Register Descriptions NONSPEC_VLD[7:0] SEQCOUNT AMD Geode™ LX Processors Data Book...
Page 123 0: Target RAM BIST did not pass. (Default) 1: Target RAM BIST passed. TAG_PASS Tag RAM BIST Status. 0: Tag RAM BIST did not pass. (Default) 1: Tar RAM BIST passed. AMD Geode™ LX Processors Data Book IF_BIST_MSR Register Map RSVD RSVD IF_BIST_MSR Bit Descriptions 33234H...
Page 124 Suspend on Halt. When set, if the processor is halted, then it requests that its clocks be turned off. (Default = 0) XC_CONFIG_MSR Register Map RSVD RSVD XC_CONFIG_MSR Bit Descriptions CPU Core Register Descriptions AMD Geode™ LX Processors Data Book...
Page 125 DMM_ACTIVE Debug Management Mode. Processor is in debug management mode. (Default = 0) SMM_ACTIVE System Management Mode. Processor is in system management mode. (Default = 0) AMD Geode™ LX Processors Data Book XC_MODE_MSR Register Map RSVD XC_MODE_MSR Bit Descriptions 33234H...
Page 126: Table 5-14. Xc_Hist_Msr Exception Types
CPU Core Register Descriptions TYPE7 TYPE6 TYPE1 TYPE0 Value Description External system management during I/O instruction External system management Init Reset Internal suspend/stall External suspend/stall Unsuspend/unstall Triple fault shutdown External maskable interrupt No exception AMD Geode™ LX Processors Data Book...
Page 127 Test Registers. 0: Disable. (Default) 1: Enable. INV_3DNOW Inverse 3DNow!™. Inverse AMD 3DNow!™ instructions PFRCPV and RFRSQRTV. 0: Disable. 1: Enable. (Default) SERIAL Serialize. Serialize the CPU integer pipeline by only allowing one instruction in the pipe- line at a time.
Page 128 Enable Suspend during SMM. Enable Suspend during SMM mode. 0: Disable. 1: Enable. SMM_NMI Enable Non-Maskable Interrupts during SMM. Enable NMI during SMM mode. 0: Disable. 1: Enable. SMM_CTL_MSR Register Map RSVD RSVD SMM_CTL_MSR Bit Descriptions CPU Core Register Descriptions AMD Geode™ LX Processors Data Book...
Page 129 DMI_EXT Enable External TDBGI Pin. Enable DMIs caused by the TDBGI pin (ball AB2) when not in DMM. 0: Disable. 1: Enable. AMD Geode™ LX Processors Data Book DMI Control Register Map RSVD RSVD DMI Control Register Bit Descriptions 33234H...
Page 130 Temporary 2 MSR (TEMP2_MSR) MSR Address Type Reset Value Temporary 3 MSR (TEMP3_MSR) MSR Address Type Reset Value TEMPx_MSR Register Map RSVD TEMPx TEMPx_MSR Bit Descriptions CPU Core Register Descriptions 00001312h xxxxxxxx_xxxxxxxxh 00001313h xxxxxxxx_xxxxxxxxh AMD Geode™ LX Processors Data Book...
Page 131 Available. Bit available for operating system use. 27:24 RSVD Reserved. Present. 22:21 Descriptor Privilege Level. Non-System Descriptor. AMD Geode™ LX Processors Data Book LDT Segment Selector/Flags Register (LDT_SEL_MSR) MSR Address Type Reset Value Temp Segment Selector/Flags Register (TM_SEL_MSR) MSR Address Type...
Page 132 SMM_HDR SMM Header. Address that indicates where SMI data is written. SMI data is written at lower addresses than SMM_HDR (negative offsets). SMM_HDR_MSR Register Map RSVD SMM_HDR SMM_HDR_MSR Bit Descriptions CPU Core Register Descriptions AMD Geode™ LX Processors Data Book...
Page 133 Reserved. Write as read. 31:0 DMM_HDR DMM Header. Address that indicates where DMI data is written. DMI data is written at lower addresses than DMM_HDR (negative offsets). AMD Geode™ LX Processors Data Book DMM_HDR_MSR Register Map RSVD DMM_HDR DMM_HDR_MSR Bit Descriptions...
Page 134 DMM Segment Base/ Limit MSR (DMM_BASE_MSR) MSR Address Type Reset Value Segment Base/Limit MSR Register Map LIMIT BASE CPU Core Register Descriptions 00001337h xxxxxxxx_xxxxxxxxh 00001338h xxxxxxxx_xxxxxxxxh 00001339h xxxxxxxx_xxxxxxxxh 0000133Ah xxxxxxxx_xxxxxxxxh 0000133Bh xxxxxxxx_xxxxxxxxh 0000133Ch xxxxxxxx_xxxxxxxxh AMD Geode™ LX Processors Data Book...
Page 135 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Name Description 63:32 Breakpoint 3 I/O Port Number/Linear Address. 31:0 Breakpoint 2 I/O Port Number/Linear Address. AMD Geode™ LX Processors Data Book DR1_DR0_MSR Register Map DR1_DR0_MSR Bit Descriptions DR3_DR2_MSR Register Map DR2_DR3_MSR Bit Descriptions 33234H...
Page 136 Breakpoint 1 Matched. Breakpoint 0 Matched. DR7_DR6_MSR Register Map BT BS BD DR7_DR6_MSR Bit Descriptions CPU Core Register Descriptions RSVD G3 L3 G2 L2 G1 L1 G0 L0 RSVD (FFh) B3 B2 B1 B0 AMD Geode™ LX Processors Data Book...
Page 137 Name Description 63:32 XDR3 Extended Breakpoint 3 I/O Port Number/Linear Address. 31:0 XDR2 Extended Breakpoint 2 I/O Port Number/Linear Address. AMD Geode™ LX Processors Data Book XDR1_XDR0_MSR Register Map XDR1 XDR0 XDR1_XDR0_MSR Bit Descriptions XDR3_XDR2_MSR Register Map XDR3 XDR2 XDR3_XDR2_MSR Bit Descriptions...
Page 138 RSVD (1FFFFh) XDR5_XDR4_MSR Register Map OPCODE_MASK4 OPCODE_VALUE4 XDR5_XDR4_MSR Bit Descriptions XDR7_XDR6_MSR Register Map RSVD CPU Core Register Descriptions E6 E5 E4 E3 E2 E1 E0 RSVD (1Fh) B6 B5 B5 B3 B2 B1 B0 AMD Geode™ LX Processors Data Book...
Page 139 Reserved. Default = 1Fh. Extended Breakpoint 6 Status. Extended Breakpoint 5 Status. Extended Breakpoint 4 Status. Extended Breakpoint 3 Status. Extended Breakpoint 2 Status. Extended Breakpoint 1 Status. Extended Breakpoint 0 Status. AMD Geode™ LX Processors Data Book XDR7_XDR6_MSR Bit Descriptions 33234H...
Page 140 Address Size Prefix Value for Extended Breakpoint 5. 0F or 0F 0F Prefix Value for Extended Breakpoint 5. 23:0 OPCODE_VALUE5 Opcode Match Value for Extended Breakpoint 5. XDR9_XDR8_MSR Register Map OPCODE_MASK5 OPCODE_VALUE5 XDR9_XDR8_MSR Bit Descriptions CPU Core Register Descriptions AMD Geode™ LX Processors Data Book...
Page 141 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Name Description 63:32 RSVD Reserved. 31:0 EX_IP EX Stage Effective Instruction Pointer. AMD Geode™ LX Processors Data Book XDR11_XDR10_MSR Register Map RSVD XDR11_XDR10_MSR Bit Descriptions EX_IP_MSR Register Map RSVD EX_IP EX_IP_MSR Bit Descriptions 33234H...
Page 142 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Name Description 63:32 RSVD Reserved. 31:0 EX_LIP EX Stage Linear Instruction Pointer. WB_IP_MSR Register Map RSVD WB_IP WB_IP_MSR Bit Descriptions EX_LIP_MSR Register Map RSVD EX_LIP EX_LIP_MSR Bit Descriptions CPU Core Register Descriptions AMD Geode™ LX Processors Data Book...
Page 143 CS 1 Linear Instruction Pointer. Second most recent linear instruction point when code segment was loaded. 31:0 C0_LIP CS 0 Linear Instruction Pointer. Most recent linear instruction point when code seg- ment was loaded. AMD Geode™ LX Processors Data Book WB_LIP_MSR Register Map RSVD WB_LIP WB_LIP_MSR Bit Descriptions C1_C0_LIP_MSR Register Map...
Page 144 Code Segment. Selector of code segment of last FP instruction that may have caused an FP error. C3_C2_LIP_MSR Register Map C3_LIP C2_LIP C3_C2_LIP_MSR Bit Descriptions FPENV_CS_MSR Register Map RSVD FPENV_CS_MSR Bit Descriptions CPU Core Register Descriptions AMD Geode™ LX Processors Data Book...
Page 145 RSVD Reserved. 15:0 Data Segment. Selector of data segment of memory operand of last FP instruction that may have caused an FP error. AMD Geode™ LX Processors Data Book FPENV_IP_MSR Register Map RSVD FPENV_IP_MSR Bit Descriptions FPENV_DS_MSR Register Map RSVD...
Page 146 Opcode Pointer. Opcode of last FP instruction executed that may have caused an FP error. FPENV_DP_MSR Register Map RSVD FPENV_DP_MSR Bit Descriptions FPENV_OP_MSR Register Map RSVD RSVD FPENV_OP_MSR Bit Descriptions CPU Core Register Descriptions AMD Geode™ LX Processors Data Book...
Page 147 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Name Description 63:1 RSVD Reserved. LOCK_EN Lock Enable. Allow Address Calculation Unit (AC) to issue locked requests to Data Memory Subsystem (DM). AMD Geode™ LX Processors Data Book AC_CONFIG_MSR Register Map RSVD RSVD AC_CONFIG_MSR Bit Descriptions 33234H...
Page 148 General Register Temp 7 MSR (GR_TEMP7_MSR) MSR Address Type Reset Value General Registers MSRs Register Map RSVD GR_REG CPU Core Register Descriptions 00001410h 00000000_00000000h 00001411h 00000000_00000000h 00001412h 00000000_00000000h 00001413h 00000000_00000000h 00001414h 00000000_00000000h 00001415h 00000000_00000000h 00001416h 00000000_00000000h 00001417h 00000000_00000000h AMD Geode™ LX Processors Data Book...
Page 149 (see Section 5.5.2.74 on page 172). The contents of CR0-CR4 should only be accessed using the MOV instruction. They are mentioned here for completeness only. See Section 5.4.1 “Control Registers” on page 95 for bit descriptions. AMD Geode™ LX Processors Data Book EFLAG_MSR Register Map...
Page 150 0: Disable. Invalidate clean cache lines when replaced, do not evict. (Default) 1: Enable. Evict clean cache lines when they are replaced. RSVD Reserved. IM_CONFIG_MSR Register Map RSVD RSVD RSVD IM_CONFIG_MSR Bit Descriptions CPU Core Register Descriptions AMD Geode™ LX Processors Data Book...
Page 151 0: Enable. (Default) 1: Disable. Treatment Bus Enable. If this bit is set, then the treatment bus from the GLCP is able to modify the IM’s behavior. 0: Disable. (Default) 1: Enable AMD Geode™ LX Processors Data Book 33234H...
Page 152 WAY field in IC_INDEX_MSR. Each access to IC_DATA_MSR increments DSEL. IC_INDEX_MSR Register Map RSVD DSEL RSVD IC_INDEX_MSR Bit Descriptions IC_DATA_MSR Register Map DATA (Upper) DATA (Lower) IC_DATA_MSR Bit Descriptions CPU Core Register Descriptions LINE AMD Geode™ LX Processors Data Book...
Page 153 RSVD (RO) Reserved (Read Only). Valid. Valid bit for the line/way selected by IC_INDEX_MSR (MSR 00001710h). (Default = 0) AMD Geode™ LX Processors Data Book IC_TAG_MSR MSR Register Map IC_TAG_MSR Bit Descriptions Ways (15-8) more recent than ways (7-0) Ways (15-12) more recent than ways (11-8)
Page 154 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 TLB_NUM IC_TAG_I_MSR Register Map IC_TAG_I_MSR Bit Descriptions L0_IC_DATA_MSR Register Map DATA (Upper) DATA (Lower) L0_IC_DATA_MSR Bit Descriptions L0_IC_TAG_I_MSR Register Map RSVD RSVD CPU Core Register Descriptions RSVD LINE RSVD AMD Geode™ LX Processors Data Book...
Page 155 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bits Name Description 63:4 RSVD Reserved. INDEX Index. AMD Geode™ LX Processors Data Book L0_IC_TAG_I_MSR Bit Descriptions ITB_INDEX_MSR Register Map RSVD RSVD ITB_INDEX_MSR Bit Descriptions 33234H INDEX...
Page 156 Bit 1: Entry 0 more recent than entry 2 Bit 0: Entry 0 more recent than entry 1 0: False (Default) 1: True ITB_LRU_MSR Register Map RSVD ITB_LRU_MSR Bit Descriptions CPU Core Register Descriptions AMD Geode™ LX Processors Data Book...
Page 157 0: Supervisor. 1: User. RSVD (RO) Reserved (Read Only). (Default = 0) Valid Bit. 0: Not valid. (Default) 1: Valid. AMD Geode™ LX Processors Data Book 33234H ITB L0 Cache Entry MSR (ITB_L0_ENTRY_MSR) MSR Address 00001724h Type Reset Value xxxxxxxx_xxxxxxxxh...
Page 158 Reserved (Read Only). (Default = 0) DATA Data Array BIST. 0: Fail 1: Pass IM_BIST_TAG_MSR Register Map RSVD RSVD IM_BIST_TAG_MSR Bit Descriptions IM_BIST_DATA_MSR Register Map RSVD RSVD IM_BIST_DATA_MSR Bit Descriptions CPU Core Register Descriptions AMD Geode™ LX Processors Data Book...
Page 159 000: Disable timeout. (Default) 001-111: 2**(4 + WBTO) clocks (32, 64, ..., 2048). 35:33 RSVD Reserved. (Default = 0) AMD Geode™ LX Processors Data Book DM_CONFIG0_MSR Register Map WSREQ DM_CONFIG0_MSR Bit Descriptions 33234H WCTO...
Page 160 Use DCDIS (bit 8) to disable the interrogations as well. Note that this field has been increased from 4 bits in the AMD Geode™ GX processor to 16 bits to allow for the new 16 way cache). (Default = 0) NOLOCKEVCT Do Not Evict Clean Lines Locked by LSLOCK.
Page 161 0: Loads bypass stores based on region properties. (Default) 1: All loads and stores are executed in program order. AMD Geode™ LX Processors Data Book 33234H...
Page 162 0: Disable the restricted cache feature. (Default) 1: Enable the restricted cache feature (PFXLOCK field, bits [15:0]). DM_CONFIG1_MSR Register Map ARRAYDIS DM_CONFIG1_MSR Bit Descriptions CPU Core Register Descriptions APFLOCK PFXLOCK AMD Geode™ LX Processors Data Book...
Page 163 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 PFLOCKT2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PFLOCKT0 AMD Geode™ LX Processors Data Book DM_PFLOCK_MSR Register Map 33234H PFLOCKT1...
Page 164 Note: Region Properties: Bits [7:6] = RSVD; Bit 5 = WS; Bit 4 = WC; Bit 3 = WT; Bit 2 = WP; Bit 1 = WA; Bit 0 = CD. See "Region Properties" on page 170 for further details. DM_PFLOCK_MSR Bit Descriptions RCONF_DEFAULT_MSR Register Map ROMBASE SYSTOP CPU Core Register Descriptions DEVRP SYSRP AMD Geode™ LX Processors Data Book...
Page 165 Note: Region Properties: Bits [7:6] = RSVD; Bit 5 = WS; Bit 4 = WC; Bit 3 = WT; Bit 2 = WP; Bit 1 = WA; Bit 0 = CD. See "Region Properties" on page 170 for further details. AMD Geode™ LX Processors Data Book RCONF_BYPASS_MSR Register Map...
Page 166 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RPEC RCONF_C0_DF_MSR Register Map RPD8 RPD4 RPC8 RPC4 RCONF_C0_DF_MSR Bit Descriptions RCONF_E0_FF_MSR Register Map RPF8 RPF4 RPE8 RPE4 CPU Core Register Descriptions RPD0 RPC0 RIF0 RPE0 AMD Geode™ LX Processors Data Book...
Page 167 Note: Region Properties: Bits [7:6] = RSVD; Bit 5 = WS; Bit 4 = WC; Bit 3 = WT; Bit 2 = WP; Bit 1 = WA; Bit 0 = CD. See "Region Properties" on page 170 for further details. AMD Geode™ LX Processors Data Book RCONF_E0_FF_MSR Bit Descriptions...
Page 168 Note: Region Properties: Bits [7:6] = RSVD; Bit 5 = WS; Bit 4 = WC; Bit 3 = WT; Bit 2 = WP; Bit 1 = WA; Bit 0 = CD. See "Region Properties" on page 170 for further details. RCONF_DMM_MSR Register Map CPU Core Register Descriptions RSVD RPDMM RSVD DMM_NORM AMD Geode™ LX Processors Data Book...
Page 169 Note: Region Properties: Bits [7:6] = RSVD; Bit 5 = WS; Bit 4 = WC; Bit 3 = WT; Bit 2 = WP; Bit 1 = WA; Bit 0 = CD. See "Region Properties" on page 170 for further details. AMD Geode™ LX Processors Data Book Region Configuration Range 4 MSR (RCONF4_MSR)
Page 170: Table 5-15. Region Properties Register Map
Multiple writes to the same byte results in a single write with the last value specified. Write order is not preserved; ideal for use with frame buffers. CPU Core Register Descriptions (Write-allocate) (Cache Disable) AMD Geode™ LX Processors Data Book...
Page 171 For regions that are write-com- bined, the PWT flag in the page table can be used to force write-burstable properties for selected pages. AMD Geode™ LX Processors Data Book Description Write-combined (uncacheable).
Page 172 MSR Address Type Reset Value x86 Control Register 4 MSR (CR4_MSR) MSR Address Type Reset Value DC_INDEX_MSR Register Map RSVD RSVD DC_INDEX_MSR Bit Descriptions CPU Core Register Descriptions 00001883h 00000000_xxxxxxxxh 00001884h 00000000_xxxxxxxxh DC_LINE DC_WAY AMD Geode™ LX Processors Data Book...
Page 173 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bits Name Description 63:50 RSVD (RO) Reserved (Read Only). (Default = 0) AMD Geode™ LX Processors Data Book DC_DATA_MSR Register Map DC_DATA DC_DATA DC_DATA_MSR Bit Descriptions DC_TAG_MSR Register Map DC_TAG_MSR Bit Descriptions...
Page 174 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit descriptions for this register are the same as for MSR 00001892h, except read/write of this register causes an auto- increment on DC_INDEX_MSR (MSR 00001890h). DC_TAG_I_MSR Register Map CPU Core Register Descriptions RSVD AMD Geode™ LX Processors Data Book...
Page 175 RSVD (RO) Reserved (Read Only). INDEX L1 Data TLB Index. Index of L1 Data TLB entry to access. Post increments on each access to L1TLB_ENTRY_I_MSR (MSR 0000189Bh). AMD Geode™ LX Processors Data Book SNOOP_MSR Register Map RSVD SNOOP_ADD SNOOP_MSR Bit Descriptions...
Page 176 Bit 2: Entry 4 more recent than entry 5. Bit 1: Entry 2 more recent than entry 3. Bit 0: Entry 0 more recent than entry 1. 0: False (Default) 1: True CPU Core Register Descriptions AMD Geode™ LX Processors Data Book...
Page 177 Writable Flag. 0: Page can not be written. 1: Page can be written. VALID Valid Bit. A 1 indicates that the entry in the TLB is valid. AMD Geode™ LX Processors Data Book L1DTLB_ENTRY_MSR Register Map L1DTLB_ENTRY_MSR Bit Descriptions 33234H RSVD...
Page 178 10: DTE cache (12 entries, values 0-11). 11: 4M PTE cache (4 entries, values 0-3). L1DTLB_ENTRY_I_MSR Register Map L2TLB_INDEX_MSR Register Map RSVD L2TLB_INDEX_MSR Bit Descriptions CPU Core Register Descriptions RSVD RSVD RSVD INDEX INDEX AMD Geode™ LX Processors Data Book...
Page 179 Bit 32: DTE entry 2 more recent than entry 3. 0: False (Default) 1: True 31:22 RSVD (RO) Reserved (Read Only). (Default = 0) AMD Geode™ LX Processors Data Book L2TLB_LRU_MSR Register Map DTE_LRU PTE_LRU L2TLB_LRU_MSR Bit Descriptions 33234H RSVD...
Page 180 PHYSADDR Physical Address. Address [32:12] 11:9 RSVD (RO) Reserved (Read Only). GLOBAL Global Page Flag. A 1 indicates a global page. L2TLB_ENTRY_MSR Register Map L2TLB_ENTRY_MSR Bit Descriptions CPU Core Register Descriptions RSVD RSVD RSVD AMD Geode™ LX Processors Data Book...
Page 181 User Access Privileges. 0: Supervisor. 1: User. Writable Flag. 0: Page can not be written. 1: Page can be written. VALID Valid Bit. A 1 indicates that the entry in the TLB is valid. AMD Geode™ LX Processors Data Book 33234H...
Page 182 DATA[3:0] (RO) Data Cache Data (Read Only). BIST results for data cache data arrays[3:0]. 0: Fail. 1: Pass. 23:6 RSVD (RO) Reserved (Read Only). Read as 0. L2TLB_ENTRY_I_MSR Register Map DM_BIST_MSR Register Map RSVD DM_BIST_MSR Bit Descriptions CPU Core Register Descriptions RSVD RSVD TAGDAT AMD Geode™ LX Processors Data Book...
Page 183 GPF_X General Protection Faults on EXCEPT Flags. Generate general protection faults on MSR accesses whose response packets have the EXCEPT flag set. 0: Disable. 1: Enable. AMD Geode™ LX Processors Data Book DM_BIST_MSR Bit Descriptions BC_CONFIG0_MSR Register Map RSVD RSVD...
Page 184 IM to the DM cache. 0: Disable. 1: Enable. (Default) 5.5.2.90 Bus Controller Configuration 1 MSR (BC_CONFIG1_MSR) MSR Address 00001901h Type Reset Value 00000000_00000000h This register is reserved. Write as read. CPU Core Register Descriptions AMD Geode™ LX Processors Data Book...
Page 185 Note that a write or read to a locked MSR register causes a protection exception in the pipeline. When MSRs are locked, no GLBus MSR transactions are generated (GLBus MSR addresses are above 3FFFh). AMD Geode™ LX Processors Data Book RSVD_STS_MSR Bit Descriptions MSR_LOCK_MSR Register Map RSVD...
Page 186 Time Stamp Counter Low DWORD. This field provides a synchronized snapshot of the low DWORD of the TSC register (MSR 00000010h). RTSC_MSR Register Map RTSC (High DWORD) RTSC (Low DWORD) RTSC_MSR Bit Descriptions RTSC_TSC_MSR Register Map RTSC_LOW TSC_LOW RTSC_TSC_MSR Bit Descriptions CPU Core Register Descriptions AMD Geode™ LX Processors Data Book...
Page 187 L2 Cache Allocation Enable. A new line is allocated into the L2 cache only if this bit is on (Default = 1) L2_EN L2 Cache Enable. If this bit is on, the arbiter redirects memory accesses to the L2 block. (Default = 0) AMD Geode™ LX Processors Data Book L2_CONFIG_MSR Register Map RSVD L2_DM_LOCK RSVD...
Page 188 Reserved. (Default = 0) L2_WAY L2 Cache Way Selected for Diagnostics Accesses. (Default = 0) L2_STATUS_MSR Register Map RSVD RSVD L2_STATUS_MSR Bit Descriptions L2_INDEX_MSR Register Map RSVD L2_INDEX_MSR Bit Descriptions CPU Core Register Descriptions L2_INDEX RSVD AMD Geode™ LX Processors Data Book...
Page 189 Reserved. (Default = 0) L2_VALID L2 Cache Valid. Valid bit for the current way. 0: Invalid. (Default) 1: Valid. AMD Geode™ LX Processors Data Book L2_DATA_MSR Register Map L2_DATA (High DWORD) L2_DATA (Low DWORD) L2_DATA_MSR Bit Descriptions L2_TAG_MSR Register Map...
Page 190 BIST_TAG_GO_ L2 Cache Tag Comparator BIST Result (Read Only). CMP (RO) 0: Fail. (Default) 1: Pass. L2_TAG_I_MSR Register Map RSVD RSVD L2_BIST_MSR Register Map RSVD L2_BIST_MSR Bit Descriptions CPU Core Register Descriptions L2_MRU RSVD AMD Geode™ LX Processors Data Book...
Page 191 L2 Cache Tag Data Retention Timer BIST Enable. Enable Data Retention timer for DRT_EN the Tag BIST. 0: Disable. (Default) 1: Enable BIST_TAG_EN L2 Cache Tag BIST Enable. Start Tag BIST (on a write). 0: Don’t start BIST. (Default) 1: Start BIST AMD Geode™ LX Processors Data Book 33234H...
Page 192 0: Disable. (Default) 1: Enable. L2_INVAL_EN L2 Cache Invalidate Enable. Allows L2 cache invalidation through the treatment bus. 0: Disable. (Default) 1: Enable. L2_TRTMNT_CTL_MSR Register Map RSVD CPU Core Register Descriptions RSVD AMD Geode™ LX Processors Data Book...
Page 193 BCL2_MSR is idle. (Default = 0) BCL2_GATED BCL2 Gated. When bit is set, BCL2 may turn off the clock to BC Region 2 when BCL2 is idle. (Default = 0) AMD Geode™ LX Processors Data Book PMODE_MSR Register Map RSVD RSVD...
Page 194 (Default = 0) BXDR1_BXDR0_MSR Register Map BXDR1_PHYS_ADDR BXDR0_PHYS_ADDR BXDR1_BXDR0_MSR Bit Descriptions BXDR3_BXDR2_MSR Register Map BXDR3_PHYS_ADDR BXDR2_PHYS_ADDR BXDR3_BXDR2_MSR Bit Descriptions CPU Core Register Descriptions AMD Geode™ LX Processors Data Book...
Page 195 Extended Breakpoint 2 Length. Selects the size of extended breakpoint 2. See LEN3 (bits [47:46]) for decode. 43:42 LEN1 Extended Breakpoint 1 Length. Selects the size of extended breakpoint 0. See LEN3 (bits [47:46]) for decode. AMD Geode™ LX Processors Data Book BXDR6_BXDR7_MSR Register Map TYPE0 LEN3 LEN2 RSVD...
Page 196 Extended Breakpoint 1 Triggered. A 1 Indicates that extended breakpoint 1 has trig- gered. Write to clear. (Default = 0) Extended Breakpoint 0 Triggered. A 1 Indicates that extended breakpoint 0 has trig- gered. Write to clear. (Default = 0) CPU Core Register Descriptions AMD Geode™ LX Processors Data Book...
Page 197 RSVD Reserved. (Default = 0) 31:0 PHYS_ADDR Address Match Value for BDRx. (Default = 0) AMD Geode™ LX Processors Data Book Bus Controller Debug Register 2 MSR (BDR2_MSR) MSR Address Type Reset Value Bus Controller Debug Register 3 MSR (BDR3_MSR)
Page 198 RSVD Reserved. (Default = 0) BDR6_MSR Register Map RSVD RSVD BDR6_MSR Bit Descriptions BDR7_MSR Register Map RSVD TYPE0 RSVD BDR7_MSR Bit Descriptions CPU Core Register Descriptions T3 T2 T1 T0 E3 E2 E1 E0 AMD Geode™ LX Processors Data Book...
Page 199 1: Enable. Breakpoint 1 Enable. Allows extended breakpoint 1 to be enabled. 0: Disable. 1: Enable. Breakpoint 0 Enable. Allows extended breakpoint 0 to be enabled. 0: Disable. 1: Enable. AMD Geode™ LX Processors Data Book BDR7_MSR Bit Descriptions 33234H...
Page 200 Data Memory Subsystem L2 TLB 1 Delay Control. (Default = 1) L2TB0 Data Memory Subsystem L2 TLB 0 Delay Control. (Default = 1) RSVD RSVD MSS_ARRAY_CTL0_MSR Register Map RSVD DMTAG1 CPU Core Register Descriptions DMDATA1 DMTAG0 L2TLB1 L2TLB0 AMD Geode™ LX Processors Data Book...
Page 201 L2 Cache Tag 2 Delay Setting. (Default = 3) 11:6 L2TAG1 L2 Cache Tag 1 Delay Setting. (Default = 3) L2TAG0 L2 Cache Tag 0 Delay Setting. (Default = 3) AMD Geode™ LX Processors Data Book MSS_ARRAY_CTL1_MSR Register Map RSVD IMDATA0 MSS_ARRAY_CTL2_MSR Register Map RSVD...
Page 202 5.5.2.116 FPU Reserved MSR (FPU_RSVD_MSR) MSR Address 00001A03h Type Reset Value 00000000_00000000h This register is reserved for internal testing; do not write. FP_MODE_MSR Register Map RSVD RSVD FP_MODE_MSR Bit Descriptions CPU Core Register Descriptions AMD Geode™ LX Processors Data Book...
Page 203 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD AMD Geode™ LX Processors Data Book FPU_CW_MSR Register Map RSVD...
Page 204 FPU Register Map. Internal mapping of architectural registers to physical registers in the register array. FPU_TW_MSR Bit Descriptions FPU_BUSY_MSR Register Map RSVD RSVD FPU_BUSY_MSR Bit Descriptions FPU_MAP_MSR Register Map RSVD FPU_REG_MAP FPU_MAP_MSR Bit Descriptions CPU Core Register Descriptions AMD Geode™ LX Processors Data Book...
Page 205 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Name Description 63:0 FPU_MRx Mantissa of FPU Rx MSR. AMD Geode™ LX Processors Data Book Mantissa of R8 MSR (FPU_MR8_MSR) MSR Address Type Reset Value Mantissa of R9 MSR (FPU_MR9_MSR)
Page 206 Exponent of R15 MSR (FPU_ER15_MSR) MSR Address Type Reset Value FPU_ERx_MSR Register Map RSVD FPU_ERx FPU_ERx_MSR Bit Descriptions CPU Core Register Descriptions 00001A51h 00000000_0000xxxxh 00001A53h 00000000_0000xxxxh 00001A55h 00000000_0000xxxxh 00001A57h 00000000_0000xxxxh 00001A59h 00000000_0000xxxxh 00001A5Bh 00000000_0000xxxxh 00001A5Dh 00000000_0000xxxxh 00001A5Fh 00000000_0000xxxxh AMD Geode™ LX Processors Data Book...
Page 207 Type Reset Value 00000000_000005A1h Extended Feature Flags (CPUID9_MSR) MSR Address 00003009h Type Reset Value C0C0A13D_00000000h AMD Geode™ LX Processors Data Book 33234H CPU Marketing Name 1 (CPUIDA_MSR) MSR Address 0000300Ah Type Reset Value 4D542865_646F6547h CPU Marketing Name 2 (CPUIDB_MSR) MSR Address...
Page 208 L2 TLB Information. Same data as CPUID instruction [80000006] EBX/EAX. 63:0 CPUID13 L2 Cache Information. Same data as CPUID instruction [80000006] EDX/ECX. CPUIDx_MSR Register Map CPUIDx CPUIDx CPUIDx_MSR Bit Descriptions CPU Core Register Descriptions AMD Geode™ LX Processors Data Book...
Page 209: 6.0Integrated Functions
Integrated Functions The integrated functions of the AMD Geode™ LX proces- sor are: • GeodeLink™ Memory Controller (GLMC) • Graphics Processor (GP) • Display Controller (DC) • Video Processor (VP) • GeodeLink Control Processor (GLCP) Clock Module SYSREF System PLL...
Page 210: Geodelink™ Memory Controller
The GeodeLink™ Memory Controller (GLMC) module sup- ports the Unified Memory Architecture (UMA) of the AMD Geode™ LX processor and controls a 64-bit DDR SDRAM interface without any external buffering. The inter- nal block diagram of the GLMC is shown in Figure 6-2.
Page 211: Figure 6-3. Hoi Addressing Example
This gives a total of eight component banks in this memory configuration. Each page in a component bank is separated from the next component bank page by 8 MB. See Figure 6-4. AMD Geode™ LX Processors Data Book 33234H Internal aaaaaaaaaaaaaaaaaaaaaaaaaa...
Page 212: Figure 6-5. Loi Addressing Example
Page 0 Page 0 00018000h 0001A000h 0001C000h Page 0 Page 0 Page 0 Address Address Address Figure 6-6. LOI Example AMD Geode™ LX Processors Data Book Bank Page 0 00006000h Page 0 Address Bank Page 0 0000E000h Page 0 Address...
Page 213: Table 6-1. Loi - 2 Dimms, Same Size, 1 Dimm Bank
Address 2 Component Banks MA13 MA12 MA11 MA10 CS0#/CS1# CS2#/CS3# BA0/BA1 AMD Geode™ LX Processors Data Book 4 KB Page Size 1 KB Page Size A11/A10 4 KB Page Size 1 KB Page Size A11/A10 33234H 2 KB Page Size...
Page 214: Table 6-3. Non-Auto Loi - 1 Or 2 Dimms, Different Sizes, 1 Dimm Bank
1 KB Page Size A11/A10 GeodeLink™ Memory Controller 2 KB Page Size 4 KB Page Size 4 Component Banks A12/A11 A13/A12 2 KB Page Size 4 KB Page Size 4 Component Banks A12/A11 A13/A12 AMD Geode™ LX Processors Data Book...
Page 215: Figure 6-7. Request Pipeline
Requests from different sources may pass each other as long as the addresses do not match. AMD Geode™ LX Processors Data Book If reordering is allowable, requests may be reordered for the following reasons: A request with a higher priority can pass a request in...
Page 216: Figure 6-8. Ddr Reads
Delay Controls (GLCP_DELAY_CONTROLS)" on page 549. 6.1.1.5 Basic Timing Diagrams Figure 6-8 and Figure 6-9 on page 217 illustrate timing waveforms for DDR reads and DDR writes. Figure 6-8. DDR Reads GeodeLink™ Memory Controller AMD Geode™ LX Processors Data Book...
Page 217: Figure 6-9. Ddr Writes
WRREQX WRREQY rqin dain_ready dain_take wrx0 wrx1 dain drdywx drdyrx w_databuf_out w_dataf m_sd_data m_sd_dqs daout AMD Geode™ LX Processors Data Book wrx2 wrx3 wry0 wrx0 wrx1 wrx2 wry0 wrx3 wrx0 wrx1 wrx2 wrx3 wrx0 wrx1 wrx2 wrrespx wrrespy Figure 6-9.
Page 218 00) and RST_DLL cleared (MSR 20000018h[27] = 0). Clear TRISTATE_DIS (MSR 2000001Dh[12] = 0) to enable the GLMC TRI_STATE during idle cycles (i.e., CS[3:0]# = Fh). 10) Wait at least 200 SDCLKs before performing the first read/write operation. AMD Geode™ LX Processors Data Book (MSR...
Page 219: Geodelink™ Memory Controller Register Descriptions
Counter and CAS Control (MC_PERCNT2) 2000001Dh Clocking and Debug (MC_CFCLK_DBUG) 2000001Eh Page Open Status (MC_CFPG_OPEN) AMD Geode™ LX Processors Data Book 33234H tables that include reset values and page references where the bit descriptions are provided. Note: MSR addresses are documented using the CPU Core as the source.
Page 220 63:24 RSVD Reserved. 23:8 DEV_ID Device ID. Identifies device (0204). REV_ID Revision ID. Identifies device revision. See AMD Geode™ LX Processors Specification Update document for value. 6.2.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG) - Not Used MSR Address 20002001h Type Reset Value 00000000_00000000h This register is not used in the GLMC module.
Page 221 Error Mask 0. Masks the corresponding error in bit 16. The GLMC only implements error mask 0 that corresponds to error bit 16. This bit masks the reporting of the error event recorded in bit 16. (Default = 0h) AMD Geode™ LX Processors Data Book GLD_MSR_ERROR Register Map RSVD...
Page 222 GLD Diagnostic (GLD_MSR_DIAG) MSR Address 20002005h Type Reset Value 00000000_00000000h This register is reserved for internal use by AMD and should not be written to. GeodeLink™ Memory Controller Register Descriptions GLD_MSR_PM Register Map RSVD RSVD GLD_MSR_PM Bit Descriptions AMD Geode™ LX Processors Data Book...
Page 223 31:22 RSVD Reserved. Reads back as 0. 21:0 MC_CF_BANK2 Memory Controller Configuration Bank 2. Open row address (31:10) for Bank2, DIMM0. AMD Geode™ LX Processors Data Book MC_CF_BANK01 Register Map MC_CF_BANK1 MC_CF_BANK0 MC_CF_BANK01 Bit Descriptions MC_CF_BANK23 Register Map MC_CF_BANK3 MC_CF_BANK2...
Page 224 Memory Controller Configuration Bank 6. Open row address (31:10) for Bank6, DIMM0. GeodeLink™ Memory Controller Register Descriptions MC_CF_BANK45 Register Map MC_CF_BANK5 MC_CF_BANK4 MC_CF_BANK45 escriptions Bit D MC_CF_BANK67 Register Map MC_CF_BANK7 MC_CF_BANK6 MC_CF_BANK67 Bit Descriptions AMD Geode™ LX Processors Data Book...
Page 225 31:22 RSVD Reserved. Reads back as 0. 21:0 MC_CF_BANKA Memory Controller Configuration Bank A. Open row address (31:10) for Bank2, DIMM1. AMD Geode™ LX Processors Data Book MC_CF_BANK89 Register Map MC_CF_BANK9 MC_CF_BANK8 MC_CF_BANK89 Bit Descriptions MC_CF_BANKAB Register Map MC_CF_BANKB MC_CF_BANKA...
Page 226 MC_CF_BANKE Memory Controller Configuration Bank E. Open row address (31:10) for Bank6, DIMM1. GeodeLink™ Memory Controller Register Descriptions MC_CF_BANKCD Register Map MC_CF_BANKD MC_CF_BANKC MC_CF_BANKCD Bit Descriptions MC_CF_BANKEF Register Map MC_CF_BANKF MC_CF_BANKE MC_CF_BANKEF Bit Descriptions AMD Geode™ LX Processors Data Book...
Page 227 D0_MB DIMM0 Module Banks. Number of module banks for DIMM0. 0: 1 Module bank. (Default) 1: 2 Module banks. 39:37 RSVD Reserved. AMD Geode™ LX Processors Data Book MC_CF07_DATA Register Map D1_PSZ D0_SZ REF_INT MC_CF07_DATA Bit Descriptions 0100: 64 MB...
Page 228 8 refresh requests, thus forcing a refresh request out to DRAM. This bit should only be used for initialization and test. (Default = 0) GeodeLink™ Memory Controller Register Descriptions 100: 16 KB 101: 32 KB 110: Reserved 111: DIMM0 Not Installed (Default) AMD Geode™ LX Processors Data Book...
Page 229 STALE_REQ RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CAS_LAT ACT2ACTREF ACT2PRE AMD Geode™ LX Processors Data Book MC_CF8F_DATA Register Map RSVD PRE2ACT ACT2CMD ACT2ACT...
Page 230 Delay Time from Act To read/WRITE. tRCD. Minimum number of SDRAM clocks between ACT and READ/WRITE commands. (6..2 valid). (Default = 011) GeodeLink™ Memory Controller Register Descriptions MC_CF8F_DATA Bit Descriptions 010: 2 (Default) 100: 4 011: 3 101: 1.5 110: 2.5 111: 3.5 AMD Geode™ LX Processors Data Book...
Page 231 DRAM. This is to satisfy a 200-clock delay from self-refresh exit to first read command (although this bit will delay all commands, read and write). (Default = 0, No delay) RSVD Reserved. AMD Geode™ LX Processors Data Book MC_CF1017_DATA Register Map RSVD REF2ACT PM1_UP_DLY...
Page 232 Events are specified in CNT1_DATA (MSR 2000001Ch[23:16]. Reset and stop con- trol on this counter is done via MSR 200001Ch[35:34]. (Default = 0h) GeodeLink™ Memory Controller Register Descriptions MC_CF1017_DATA Bit Descriptions MC_CFPERF_CNT1 Register Map CNT1 CNT0 MC_CFPERF_CNT1 Bit Descriptions AMD Geode™ LX Processors Data Book...
Page 233 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD AMD Geode™ LX Processors Data Book MC_PERFCNT2 Register Map RSVD...
Page 234 Control Mask 0. Mask output enable bit for DIMM0’s CAS0#, RAS0#, W0#, CS[1:0]#. 0: Unmasked. (Default) 1: Masked. ADRS_MSK Address Mask. Mask output enable bit for MA and BA. (Default = 0) RSVD Reserved. GeodeLink™ Memory Controller Register Descriptions MC_CFCLK_DBUG Bit Descriptions AMD Geode™ LX Processors Data Book...
Page 235 6.2.2.16 Reserved Register MSR Address 2000001Fh Type Reset Value 00000000_00000000h This register is reserved and should not be written to. AMD Geode™ LX Processors Data Book MC_CFPG_OPEN Register Map RSVD PGOPEN1 MC_CFPG_OPEN Bit Descriptions 33234H PGOPEN0...
Page 236 PMode0 is not entered. (Default = 6h, to allow 32-bit bursts to finish). GeodeLink™ Memory Controller Register Descriptions MC_CF_PMCTR Register Map PM1_SENS PM0_SENS MC_CF_PMCTR Bit Descriptions AMD Geode™ LX Processors Data Book...
Page 237: Graphics Processor
Graphics Processor Graphics Processor The Graphics Processor is based on the graphics proces- sor used in the AMD Geode™ GX processor with several features added to enhance performance and functionality. Like its predecessor, the AMD Geode LX processor’s Graphics Processor is a BitBLT/vector engine that supports...
Page 238: Table 6-7. Graphics Processor Feature Comparison
8x8 pixels Yes (with inversion) 8, 16, 32-bpp Monochrome Monochrome Y with mask Vertical and Horizontal Yes (constant α, α/pix, or sep. α channel) Decodes VGA Register Unlimited 8, 16, 32-bpp 5:6:5, 1:5:5:5, 4:4:4:4, 8:8:8:8 AMD Geode™ LX Processors Data Book...
Page 239: Table 6-8. Blt Command Buffer Structure
Graphics Processor 6.3.1 Command Buffer The AMD Geode LX processor supports a command buffer interface in addition to the normal two-deep pipelined regis- ter interface. It is advised that software use either the com- mand buffer interface or the register interface. It is possible to use both, however, all pending operations should be allowed to complete before making the switch.
Page 240: Table 6-9. Vector Command Buffer Structure
RSVD GP_LUT_INDEX Data Optional Data Word 0 Optional Data Word 1 Optional Data Word n RSVD Optional Data Word 0 Optional Data Word 1 Optional Data Word n Graphics Processor Write Enables DCOUNT DCOUNT AMD Geode™ LX Processors Data Book...
Page 241: Table 6-12. Bit Descriptions
BLT is complete, the extra pixels are discarded and the overflow bit is set in GP_BLT_STATUS. AMD Geode™ LX Processors Data Book Table 6-12. Bit Descriptions Channel 3 has the ability to begin prefetching data for a pending BLT before the active BLT has completed.
Page 242 DWORD boundary. BGR conversion is not possible in this format since this operation is done before the depth con- version. 24-bpp images may not be rotated, they would need to be converted into another format first. register, Memory Offset Graphics Processor AMD Geode™ LX Processors Data Book...
Page 243: Table 6-13. Pixel Ordering For 4-Bit Pixels
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Pixel 6 Pixel 7 Pixel 4 AMD Geode™ LX Processors Data Book address automatically increments with every write. Addresses 00h-FFh are used for 8-bpp indexed pixels and addresses 00h-0Fh are used for 4-bpp indexed pixels. The...
Page 244: Figure 6-11. 14-Bit Repeated Pattern
Table 6-14. Example Vector Pattern Table 6-15. Example Vector Length Figure 6-11. 14-Bit Repeated Pattern Graphics Processor AMD Geode™ LX Processors Data Book...
Page 245 A and B chan- nel. In all other cases, performance will be higher if destination is fetched on either the source channel or chan- nel 3. AMD Geode™ LX Processors Data Book 33234H 6.3.3 BLT Operation...
Page 246 GP_PAT_DATA_1 registers, with row 0 loaded into GP_PAT_DATA_0 (GP Memory Offset 30h[7:0] (bit 7 being the left-most pixel on the screen)), and row 7 loaded into GP_PAT_DATA_1 (GP Memory Offset 34h[31:24], see Table 6-16). AMD Geode™ LX Processors Data Book Graphics Processor specified...
Page 247: Table 6-16. Example Of Monochrome Pattern
GP_PAT_DATA_1[15:8] - 22h GP_PAT_DATA_1[23:16] - 14h GP_PAT_DATA_1[31:24] - 08h AMD Geode™ LX Processors Data Book would be BLTed during the first pass, and all of the odd lines during the second pass. The pattern registers should be programmed with the even lines on the first pass and...
Page 248: Table 6-17. Example Of 8-Bit Color Pattern (3:3:2 Format)
Byte Byte 13:12 11:10 0010 0010 4000 0010 0010 4000 F81F 4000 Graphics Processor Byte 3 Byte 2 Byte 1 Byte Byte Byte 4000 0010 4000 0010 4000 F81F AMD Geode™ LX Processors Data Book Byte 0 Byte 0010 4000...
Page 249: Table 6-19. 32-Bpp 8:8:8:8 Color Data Format
Byte 3 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 8 Right Most Pixel AMD Geode™ LX Processors Data Book GP_RASTER_MODE 38h[31:28]), then the pattern is translated to the depth specified by the GP_RASTER_MODE register.
Page 250: Table 6-23. Example Of Byte-Packed Monochrome Source Data
00 01 02 03 04 05 20 21 22 23 24 25 40 41 42 43 44 45 Byte 0 00 01 02 03 04 05 10 1 1 12 13 14 15 20 21 22 23 24 25 AMD Geode™ LX Processors Data Book...
Page 251: Table 6-25. Gp_Raster_Mode Bit Patterns
Table 6-25. GP_RASTER_MODE Bit Patterns Pattern (bit) Source (bit) AMD Geode™ LX Processors Data Book GP_SRC_COLOR_FG is loaded with 03h (hardware expands GP_SRC_COLOR_BG (GP Memory Offset 14h) is loaded with FFh (perform compare on all bits). To make all pixels...
Page 252: Table 6-27. Alpha Blending Modes
Description Resulting image is clear. Display only one of the images (or multiply an image by its alpha). Α Graphics Processor , is specified or α yields indeterminate AS Bits OS Bits (00) (00) AMD Geode™ LX Processors Data Book...
Page 253 α fade A α fade A plus fade B A plus B AMD Geode™ LX Processors Data Book Description 1-α Display image A on top of image Α B. Wherever image A is transpar- ent, display image B. Use image B to mask image A.
Page 254: Graphics Processor Register Definitions
Register Name Destination Offset (GP_DST_OFFSET) Source Offset (GP_SRC_OFFSET) Vector Error (GP_VEC_ERR) Stride (GP_STRIDE) BLT Width/Height (GP_WID_HEIGHT) Vector Length (GP_VEC_LEN) AMD Geode™ LX Processors Data Book GP_BLT_STATUS, Reference Page 256 Page 256 Page 257 Page 257 Page 258 Page 258 Reset Value...
Page 255 Channel3 Channel3 Channel3 Channel3 Channel3 Channel3 Interrupt Control 3FF:100h BLT Data FFF:400h Channel3 AMD Geode™ LX Processors Data Book Register Name Source Color Foreground (GP_SRC_COLOR_FG) Source Color Background (GP_SRC_COLOR_BG) Pattern Color (GP_PAT_COLOR_x) Pattern Data (GP_PAT_DATA_x) Raster Mode (GP_RASTER_MODE) Vector Mode...
Page 256 CLKDOM Clock Domain. Number of clock domains. The GP has one clock domain. 23:8 Device ID. Identifies device (03D4h). Revision ID. Identifies device revision. See AMD Geode™ LX Processors Specification Update document for value. 6.4.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG)
Page 257 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 RSVD AMD Geode™ LX Processors Data Book GLD_MSR_SMI Register Map RSVD...
Page 258 GLD Diagnostic MSR (GLD_MSR_DIAG) MSR Address A0002005h Type Reset Value 00000000_00000000h This register is reserved for internal use by AMD and should not be written to. GLD_MSR_ERROR Bit Descriptions GLD_MSR_PM Register Map RSVD RSVD GLD_MSR_PM Bit Descriptions Graphics Processor Register Definitions...
Page 259 Name Description 31:29 RSVD Reserved. Write as read. 28:26 XLSBS X LSBs. Offset within byte to first monochrome pixel. AMD Geode™ LX Processors Data Book GP_DST_OFFSET Register Map OFFSET GP_DST_OFFSET Bit Descriptions GP_SRC_OFFSET Register Map OFFSET GP_SRC_OFFSET Bit Descriptions 33234H...
Page 260 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 S_STRIDE GP_VEC_ERR Register Map GP_VEC_ERR Bit Description GP_STRIDE Register Map Graphics Processor Register Definitions D_ERR D_STRIDE AMD Geode™ LX Processors Data Book...
Page 261 27:16 Length. Length of the vector in pixels. 15:0 I_ERR Initial Error. Initial error for rendering a vector (2’s complement format). AMD Geode™ LX Processors Data Book GP_STRIDE Bit Descriptions GP_WID_HEIGHT Register Map RSVD GP_WID_HEIGHT Bit Descriptions GP_VEC_LEN Register Map...
Page 262 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Name Description 31:0 SRC_FG Source Foreground. Mono source mode: Foreground source color. Color source mode: Color key for transparency. GP_SRC_COLOR_FG Register Map SRC _FG GP_SRC_COLOR_FG Bit Descriptions Graphics Processor Register Definitions AMD Geode™ LX Processors Data Book...
Page 263 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Name Description 31:0 SRC_BG Source Background. Mono source mode: Background source color. Color source mode: Color key mask for transparency. AMD Geode™ LX Processors Data Book GP_SRC_COLOR_BG Register Map SRC _BG GP_SRC_COLOR_BG Bit Descriptions 33234H...
Page 264: Table 6-30. Pat_Color Usage For Color Patterns
PAT_COLOR_x GP_PAT_COLOR_x Bit Descriptions Graphics Processor Register Definitions 32-bpp Mode Line 0, pixel 2 Line 0, pixel 3 Line 0, pixel 4 Line 0, pixel 5 Line 0, pixel 6 Line 0, pixel 7 AMD Geode™ LX Processors Data Book...
Page 265: Table 6-31. Pat_Data Usage For Color Patterns
ROP and other control bits without having to rewrite the BPP and FMT every time. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 BPP/FMT RSVD AMD Geode™ LX Processors Data Book 8-bpp Mode 16-bpp Mode Line 0, pixels 3-0...
Page 266 00: Solid pattern. Pattern data always sourced from GP_PAT_COLOR_0 (GP Memory Offset 18h). 01: Mono pattern. 10: Color pattern. 11: Undefined. GP_RASTER_MODE Bit Descriptions 100: Color 101: Color 110: a 111: Constant 1 Graphics Processor Register Definitions AMD Geode™ LX Processors Data Book...
Page 267 1: Positive major axis step Y Major. 0: X major vector. 1: Y major vector. AMD Geode™ LX Processors Data Book ). Alpha value that can be used for some of the alpha compositing oper- GP_VECTOR_MODE Register Map RSVD GP_VECTOR_MODE Bit Descriptions...
Page 268 1: Indicates that destination data is needed from frame buffer. Source Required. 00: No source data. 01: Source from frame buffer. 10: Source from GP_HST_SRC register (GP Memory Offset 48h). 11: Undefined. GP_BLT_MODE Register Map GP_BLT_MODE Bit Descriptions Graphics Processor Register Definitions RSVD AMD Geode™ LX Processors Data Book...
Page 269 MOVS instruction. The GP throttles the incoming data by holding off register writes on the GLIU when the source FIFO is full. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 AMD Geode™ LX Processors Data Book GP_BLT_STATUS Register Map RSVD...
Page 270 Command Top. Starting address of the command buffer in the command buffer region. RSVD Reserved. Read returns 0. GP_HST_SRC Bit Descriptions GP_BASE_OFFSET Register Map SBASE GP_BASE_OFFSET Bit Descriptions GP_CMD_TOP Register Map CMD_TOP GP_CMD_TOP Bit Descriptions Graphics Processor Register Definitions CH3BASE RSVD RSVD AMD Geode™ LX Processors Data Book...
Page 271 31:24 RSVD Reserved. Read returns 0. 23:0 CMD_READ Command Read. Pointer to the tail of the command buffer in the command buffer region. AMD Geode™ LX Processors Data Book GP_CMD_BOT Register Map CMD_BOT GP_CMD_BOT Bit Descriptions GP_CMD_READ Register Map CMD_READ...
Page 272 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 YLSBS XLSBS GP_CMD_WRITE Register Map CMD_WRITE GP_CMD_WRITE Bit Descriptions GP_CH3_OFFSET Register Map OFFSET Graphics Processor Register Definitions AMD Geode™ LX Processors Data Book...
Page 273 Pipeline Select. 0: Channel 3 data directed to/replaces old pattern pipeline. 1: Channel 3 data directed to/replaces old source pipeline AMD Geode™ LX Processors Data Book GP_CH3_OFFSET Bit Descriptions GP_CH3_MODE_STR Register Map 21 20 19 18 17 16 15 14 13 12 11 10...
Page 274 Prefetch Enable. When this bit is set, data may be fetched while the BLT is still pending. Host Source. 0: Data fetched from memory. 1: Data written through host source writes. 17:16 RSVD Reserved. 15:0 STRIDE Stride. Increment between lines of bitmap in bytes. Graphics Processor Register Definitions AMD Geode™ LX Processors Data Book...
Page 275 GP using the repeat MOVS instruction. Name Description 31:0 HST_SRC Host Source Data. Used during BLT in host source mode AMD Geode™ LX Processors Data Book GP_CH3_WIDHI Register Map RSVD GP_CH3_WIDHI Bit Descriptions GP_CH3_HSRC Register Map HST_SRC...
Page 276 LUT_DATA. Used to store data into the LUT for indexed color translations and color pat- terns. GP_CH3_HSRC Register Map RSVD GP_CH3_HSRC Bit Descriptions GP_CH3_HSRC Register Map LUT_DATA GP_CH3_HSRC Bit Descriptions Graphics Processor Register Definitions LUT_INDEX AMD Geode™ LX Processors Data Book...
Page 277 GP Idle Detect Interrupt. Command Buffer Empty Detect Interrupt. 15:2 RSVD Reserved. Read returns 1. GP Idle Mask Bit. Command Buffer Empty Mask Bit. AMD Geode™ LX Processors Data Book GP_INT_CNTRL Register Map I1 I0 GP_INT_CNTRL Bit Descriptions 33234H RSVD M1 M0...
Page 278: Display Controller
GLIU0 Memory Port and Control Dirty/Valid Flags Graphics Pixel, Syncs, DISPEN Scaler/ CLUT Filter Video Data Output to VP Display Memory I/F Host I/F FIFO FIFO Display Controller GeodeLink™ GLIU0 Port Interface Unit 0 (GLIU0) AMD Geode™ LX Processors Data Book...
Page 279: Figure 6-13. Gui Block Diagram
Timing Generator Generator VP_VSYNC CRT_HSYNC DCLK PCLK CRT_VSYNC VID_CLK ENA_DISP AMD Geode™ LX Processors Data Book systems. The GUI is optimized for high resolution and high color depth display modes. ® operating Compressor Graphics Serializer Palette RAM Decompressor (3x261x8 bit) Cursor &...
Page 280: Figure 6-14. Vga Block Diagram
Display Memory I/F Data Display Memory I/F Control VGA DAC I/O Unit Host Memory I/F Unit Figure 6-14. VGA Block Diagram Display Controller Syncs DISPEN 8-bit Pixel GUI CLUT I/O Control Host Memory I/F AMD Geode™ LX Processors Data Book...
Page 281: Table 6-32. Display Modes
8, 16, or 24/32 8, 16, or 24/32 8, 16, or 24/32 AMD Geode™ LX Processors Data Book The Minimum GLIU Frequency criteria listed in Table 6-32 must be met for quality operation of the display. This fre- quency provides sufficient memory bandwidth for the mem- ory controller to maintain reliable display refresh under all operating conditions, including the video overlay.
Page 282 148.500 Display Controller Min. GLIU Frequency (MHz) 108.000 129.600 133.500 135.000 157.500 172.800 192.000 162.000 189.000 198.000 202.500 229.500 251.182 280.640 234.000 278.400 288.000 297.000 341.349 27.000 27.000 27.000 27.000 74.750 74.750 74.750 AMD Geode™ LX Processors Data Book...
Page 283: Table 6-33. Cursor Display Encodings
Icon Color 1 - Palette Index 103h Transparent - Background Pixel Border Color - Palette Index 104h AMD Geode™ LX Processors Data Book A hardware icon overlay is also supported for applications that require a fixed sprite overlay. This is particularly useful in portable applications for display status indicators that are independent of the application that is running.
Page 284: Table 6-35. Cursor/Color Key/Alpha Interaction
ALPHA = 00 COLOR = cursor color ALPHA = FF COLOR = invert graphics color ALPHA = FF COLOR = graphics color ALPHA = 00 COLOR = cursor color ALPHA = cursor alpha AMD Geode™ LX Processors Data Book...
Page 285 DRAM unless a success- ful compression has resulted, so there is no penalty for pathological frame buffer images where the compression algorithm is sub-optimal. AMD Geode™ LX Processors Data Book 33234H 6.5.1.5 Dirty/Valid RAM The DC module incorporates the Dirty/Valid RAM (DVRAM) in the Display Controller module.
Page 286: Table 6-36. Video Bandwidth
68.7 1440 2160 64.0 1440 2160 91.1 1440 2160 75.0 1440 2160 87.5 1440 2160 Display Controller Video Port Bandwidth Required (MB/s) 45.4 68.0 62.4 93.5 54.5 81.9 77.3 116.0 69.7 98.9 148.4 92.2 AMD Geode™ LX Processors Data Book...
Page 287: Table 6-37. Yuv 4:2:0 Video Data Ordering
Y1 V Y0 U Y0 U Y1 V Y0 V Y1 U Note 1. U = Cb, V = Cr. AMD Geode™ LX Processors Data Book 6.5.2 VBI Data VBI (Video Blanking Interval) data is fetched by the DC at the start of each frame.
Page 288: Figure 6-15. Vga Frame Buffer Organization
Background Background Foreground Intensity/Font Select Foreground Foreground Frame Buffer Format Buffer Address Packed Pixel B8000h-BFFFFh Packed Pixel B8000h-BFFFFh Planar A0000h-AFFFFh Planar A0000h-AFFFFh Planar A0000h-AFFFFh Planar A0000h-AFFFFh Planar A0000h-AFFFFh Planar A0000h-AFFFFh Packed Pixel A0000h-AFFFFh Byte AMD Geode™ LX Processors Data Book...
Page 289: Figure 6-16. Graphics Controller High-Level Diagram
Each bus is 8 bits except for PIX Out, which is 4 bits. Figure 6-16. Graphics Controller High-level Diagram AMD Geode™ LX Processors Data Book read and write modes are supported that provide various forms of acceleration for VGA graphics operations. A high- level diagram of the graphics controller is shown in Figure 6-16.
Page 290: Figure 6-17. Write Mode Data Flow
Figure 6-17 shows the data flow logic that supports these modes. Rotator 31:24 23:16 Map 3 Map 2 Write Data Write Data Figure 6-17. Write Mode Data Flow Display Controller Memory Maps 15:8 Map 1 Map 0 Write Data Write Data AMD Geode™ LX Processors Data Book...
Page 291: Figure 6-18. Read Mode Data Flow
Color Compare [3:0] Color Don’t Care [3:0] ReadMode1 AMD Geode™ LX Processors Data Book to do a single color compare across eight pixels. Figure 6- 18 shows the data flow for read modes. Figure 6-19 on page 292 shows how the color compare logic in Figure 6- 18 works.
Page 292: Figure 6-19. Color Compare Operation
33234H D[7:0] Memory Data [31:0] Color Compare [3:0] Color Don’t Care [3:0] Color Compare Block Detail 31:24 23:16 8x4 Input AND Compare Result [7:0] Figure 6-19. Color Compare Operation Display Controller CCx[7:0] 15:8 AMD Geode™ LX Processors Data Book...
Page 293: Figure 6-20. Graphics Filter Block Diagram
Line Buffer Line Buffer Figure 6-20. Graphics Filter Block Diagram AMD Geode™ LX Processors Data Book Scaling is controlled by adjusting the horizontal and vertical filter scale factors (through configuration register 90). These numbers represent binary rational numbers in a 2.14 format.
Page 294 H Phase Adder 2 Pixel Latch 2 Pixel Latch Figure 6-20. Graphics Filter Block Diagram (Continued) The entire structure is replicated for each pixel component (red, green, blue, and alpha). H. Coefficient RAM AMD Geode™ LX Processors Data Book Display Controller...
Page 295: Figure 6-21. Flicker Filter And Line Buffer Path
When the flicker filter is enabled, the final Figure 6-21. Flicker Filter and Line Buffer Path AMD Geode™ LX Processors Data Book image width is dictated by this final line buffer, which is 1024 pixels wide. When the flicker filter is disabled, the two...
Page 296 6.5.8 Using the Graphics Filter From a software perspective, the AMD Geode LX proces- sor DC appears much like its predecessor in the AMD Geode GX processor design. The graphics filter is disabled by default, and the timing and addressing regis- ters operate as before.
Page 297: Table 6-42. Programming Image Sizes
Because the register value represents the image size minus 1, an additional 1 is added when these two register values are added together to retain the convention. AMD Geode™ LX Processors Data Book fields, (which would effectively line-double the resulting image).
Page 298: Figure 6-22. Interlaced Timing Settings
V_Sync_Start V_Sync_End V_Total Figure 6-22. Interlaced Timing Settings Odd Field Active Front Porch Back Porch Display Controller Even Field Active Region Front Back Porch Porch V_Active_Even_End V_Sync_Even_Start V_Sync_Even_End V_Total_Even Even Field Active Front Porch AMD Geode™ LX Processors Data Book...
Page 299: Table 6-44. Timing Register Settings For Interlaced Modes
V_Sync_Start V_Sync_End 1080i 50 Hz V_Active_End V_Total V_Sync_Start V_Sync_End AMD Geode™ LX Processors Data Book Odd Register (odd_active-1) (odd_active + odd_fp + even_bp - 1) (odd_active + odd_fp - 1) (odd_active + odd_fp + odd_vsync - 1) 33234H Even Register...
Page 300: Display Controller Register Descriptions
00000000_00000015h 00000000_00000000h Reset Value 00000000_02020202h Reset Value 00000000h 00000000h 00000000h 00000000h xxxxxxxxh xxxxxxxxh xxxxxxxxh AMD Geode™ LX Processors Data Book Reference Page 305 Page 305 Page 306 Page 308 Page 310 Page 310 Reference Page 311 Reference Page 312 Page 314...
Page 301 Video Downscaling Registers 080h DC Video Downscaling Delta (DC_VID_DS_DELTA) GLIU0 Control Registers 084h DC GLIU0 Memory Offset (DC_GLIU0_MEM_OFFSET) 088h DC Dirty/Valid RAM Control (DC_DV_CTL) AMD Geode™ LX Processors Data Book 33234H Reset Value Reference xxxxxxxxh Page 323 xxxxxxxxh Page 323 xxxxxxxxh...
Page 302 Page 347 00xxxxxxh Page 348 00000000h Page 348 00000000h Page 348 00000003h Page 349 xxxxxxxxh Page 350 xxxxxxxxh Page 351 xxxxxxxxh Page 352 xxxxxxxxh Page 352 xxxxxxxxh Page 353 xxxxxxxxh Page 354 xxxxxxxxh Page 354 AMD Geode™ LX Processors Data Book...
Page 303: Table 6-48. Vga Block Configuration Register Summary
Note 1. The I/O addresses are determined by bit 0 of the Miscellaneous Output Register. See the description of this register in Section 6.6.17.1 on page 356 for more information. AMD Geode™ LX Processors Data Book Register Name/Group VGA Miscellaneous Output...
Page 304: Table 6-50. Vga Block Extended Register Summary
ReadMemoryAperture 060h BlinkCounterCtl 061h BlinkCounter 070h VGALatchSavRes 071h DACIFSavRes Display Controller Register Descriptions Reset Value Reference Page 385 Page 385 Page 385 Page 386 Page 386 Page 386 Page 387 Page 387 Page 387 AMD Geode™ LX Processors Data Book...
Page 305 63:24 RSVD Reserved. Set to 0. 23:8 DEV_ID Device ID. Identifies device (03E4h). REV_ID Revision ID. Identifies device revision. See AMD Geode™ LX Processors Specification Update document for value. 6.6.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG) MSR Address 80002001h Type Reset Value...
Page 306 Graphics Controller Register Write SMI. Reading a 1 indicates that one or more of the VGA’s Graphics Controller registers has been written; writing a 1 to this bit clears it. GLD_MSR_SMI Register Map GLD_MSR_SMI Bit Descriptions Display Controller Register Descriptions AMD Geode™ LX Processors Data Book...
Page 307 VGA’s Attribute registers has been written. GFXIOR_MSK Graphics Controller Register Read SMI. When set to 1, disables generation of the SMI that indicates that one or more of the VGA’s Graphics Controller registers has been read. AMD Geode™ LX Processors Data Book 33234H...
Page 308 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 GLD_MSR_ERROR Register Map RSVD RSVD Display Controller Register Descriptions AMD Geode™ LX Processors Data Book...
Page 309 TYPE_ERR_MASK Unexpected Type Error Mask. When set to 1, disables generation of the asynchro- nous error signal when the DC received a GLIU0 transaction with an undefined or unexpected type. AMD Geode™ LX Processors Data Book GLD_MSR_ERROR Bit Descriptions 33234H...
Page 310 GLIU0 Device Diagnostic MSR (GLD_MSR_DIAG) MSR Address 80002005h Type Reset Value 00000000_00000000h This register is reserved for internal use by AMD and should not be written to. GLD_MSR_PM Register Map RSVD RSVD GLD_MSR_PM Bit Descriptions idle, and internally disables the GLIU0 clock whenever possible.
Page 311 63:11 RSVD Reserved. 10:8 CFIFO_CTL CFIFO RAM Delay Control. RSVD Reserved. DV_RAM_CTL DV RAM Delay Control. AMD Geode™ LX Processors Data Book SPARE_MSR Register Map RSVD RSVD SPARE_MSR Bit Descriptions DC_RAM_CTL_MSR Register Map RSVD RSVD DC_RAM_CTL_MSR Bit Descriptions 33234H RSVD...
Page 312 Read operations are always allowed. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD DC_UNLOCK Register Map Display Controller Register Descriptions DC_UNLOCK AMD Geode™ LX Processors Data Book...
Page 313 DC_GENLK_CTL DC_VID_EVEN_Y_ST_OFFSET DC_VID_EVEN_U_ST_OFFSET DC_VID_EVEN_V_ST_OFFSET DC_V_ACTIVE_EVEN_TIMING DC_V_BLANK_EVEN_TIMING DC_V_SYNC_EVEN_TIMING AMD Geode™ LX Processors Data Book DC_UNLOCK Bit Descriptions (DC Memory Offset 004h) (DC Memory Offset 008h) (DC Memory Offset 00Ch) (DC Memory Offset 010h) (DC Memory Offset 014h) (DC Memory Offset 018h)
Page 314 Note that the automatic pal- ette address increment mechanism will still operate even though the address is ignored. DC_GENERAL_CFG Register Map DFHPEL DC_GENERAL_CFG Bit Descriptions Display Controller Register Descriptions DFHPSL AMD Geode™ LX Processors Data Book...
Page 315 The value is dependent upon display mode. This field should always be non-zero and should be larger than the start level. Note that the settings in the DC_ARB_CFG register (DC Memory Offset 00Ch) can also affect the priority of requests. AMD Geode™ LX Processors Data Book 33234H...
Page 316 Display-FIFO Load Enable. 0: Disable display FIFO. 1: Enable display FIFO. Setting this bit high initiates display refresh requests to the mem- ory controller at the trailing edge of vertical sync. Display Controller Register Descriptions AMD Geode™ LX Processors Data Book...
Page 317 01), this determines how those bits are allocated to color and alpha information: For 16-bpp display format: 00: 16-bpp (RGB 5:6:5) 01: 15-bpp (RGB 5:5:5) 10: XRGB (ARGB 4:4:4) 11: Reserved AMD Geode™ LX Processors Data Book DC_DISPLAY_CFG Register Map VFHPEL VFHPSL DC_DISPLAY_CFG Bit Descriptions 33234H...
Page 318 1: Enable timing generator. This bit must be set to 0 when using VGA mode unless the filters or VGA Fixed Timings are also enabled (DC_GENERAL_CFG register, bit 18, DC Memory Offset 004h[18]). Display Controller Register Descriptions AMD Geode™ LX Processors Data Book...
Page 319 (When the scaler filter is disabled, only one logical line buffer is used, and the state of the others is ignored.) AMD Geode™ LX Processors Data Book DC_ARB_CFG Register Map...
Page 320 1 (HPEN_LB_FILL). Outside of this period, this mechanism has no effect on the priority level of outgoing DC requests on the GLIU. Display Controller Register Descriptions AMD Geode™ LX Processors Data Book...
Page 321 The memory address defined by bits [27:3] takes effect at the start of the next frame scan. The pixel offset defined by bits [2:0] is latched at the end of vertical sync and added to the pixel panning offset to determine the actual panning value. AMD Geode™ LX Processors Data Book DC_FB_ST_OFFSET OFFSET...
Page 322 32-byte aligned. Note that if there is a Y offset for the cursor pattern, the cursor start offset should be set to point to the first displayed line of the cursor pattern. DC_CB_ST_OFFSET Register Map OFFSET DC_CB_ST_OFFSET Bit Descriptions DC_CURS_ST_OFFSET Register Map OFFSET Display Controller Register Descriptions AMD Geode™ LX Processors Data Book...
Page 323 The upper 4 bits of this register are for the field count mechanism. This mechanism, which did not exist on previous AMD Geode processors, allows the DC to fetch multiple fields or frames of VIP data without requiring software intervention to move the offset.
Page 324 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD DC_VID_V_ST_OFFSET Register Map OFFSET DC_DV_TOP Register Map DV_TOP Display Controller Register Descriptions RSVD AMD Geode™ LX Processors Data Book...
Page 325 Reserved. These bits should be programmed to zero. FB_LINE_SIZE Frame Buffer Line Size. This value specifies the number of QWORDs (8-byte seg- ments) to transfer for each display line from the frame buffer. AMD Geode™ LX Processors Data Book DC_DV_TOP Bit Descriptions DC_LINE_SIZE Register Map CB_LINE_SIZE...
Page 326 Y buffer data in memory. A pitch up to 512 KB is supported to allow for vertical decimation for downscaling. DC_GFX_PITCH Register Map DC_GFX_PITCH Bit Descriptions DC_VID_YUV_PITCH Register Map DC_VID_YUV_PITCH Bit Descriptions Display Controller Register Descriptions FB_PITCH Y_PITCH AMD Geode™ LX Processors Data Book...
Page 327 Because the output is to be interlaced, the flicker filter can be used. (Use of the flicker filter is not required.) For information on the configuration bits for the flicker filter, see "DC GenLock Control (DC_GENLK_CTL)" on page 350. AMD Geode™ LX Processors Data Book 33234H // h_total = 858;...
Page 328 DC_FB_ACTIVE (DC Memory Offset 05Ch) is used to program the horizontal and verti- cal active values in the frame buffer when graphics scaling is enabled. H_ACTIVE must be set to at least 64 pixels. DC_H_ACTIVE_TIMING Register Map RSVD DC_H_ACTIVE_TIMING Bit Descriptions Display Controller Register Descriptions H_ACTIVE AMD Geode™ LX Processors Data Book...
Page 329 Unlike previous versions of the DC, this field can be programmed to any pixel granularity; it is not limited to character (8-pixel) granularity. The horizontal sync must be at least 8 pixels in width. AMD Geode™ LX Processors Data Book DC_H_BLANK_TIMING Register Map RSVD...
Page 330 If interleaved mode is enabled, this value represents half the height of the final (scaled and interleaved) displayed image. DC_H_SYNC_TIMING Bit Descriptions DC_V_ACTIVE_TIMING Register Map RSVD DC_V_ACTIVE_TIMING Bit Descriptions V_ADJUST = (V_PANEL - V_ACTIVE) / 2 Display Controller Register Descriptions V_ACTIVE AMD Geode™ LX Processors Data Book...
Page 331 AMD Geode™ LX Processors Data Book DC_V_BLANK_TIMING Register Map RSVD...
Page 332 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD Name Description 31:17 RSVD Reserved. DC_FB_ACTIVE Register Map DC_FB_ACTIVE Bit Descriptions DC_CURSOR_X Register Map X_OFFSET DC_CURSOR_X Bit Descriptions Display Controller Register Descriptions FB_V_ACTIVE CURSOR_X AMD Geode™ LX Processors Data Book...
Page 333 Several additional read only display status bits are provided to allow software to properly time the programming of registers and to detect the source of display generated interrupts. AMD Geode™ LX Processors Data Book DC_CURSOR_X Bit Descriptions DC_CURSOR_Y Register Map...
Page 334 Dot Line Count. This value is the current scan line of the display. This field is NOT syn- chronized in hardware, so software should read this value twice to ensure that the result is correct. DC_LINE_CNT/STATUS Register Map RSVD DC_LINE_CNT/STATUS Bit Descriptions Display Controller Register Descriptions DOT_LINE_CNT AMD Geode™ LX Processors Data Book...
Page 335 Note that in general, 24-bit values are loaded for all color extensions. However, if a 16-bpp mode is active, only the appropriate most significant bits are used (5:5:5 or 5:6:5). AMD Geode™ LX Processors Data Book DC_PAL_ADDRESS Register Map RSVD...
Page 336 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Name Description 31:0 DFIFO_DATA Display FIFO Diagnostic Read or Write Data. DC_PAL_DATA Register Map PAL_DATA DC_PAL_DATA Bit Descriptions DC_DFIFO_DIAG Register Map DFIFO_DATA DC_DFIFO_DIAG Bit Descriptions Display Controller Register Descriptions AMD Geode™ LX Processors Data Book...
Page 337 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Name Description 31:0 CFIFO_DATA Compressed Data FIFO Diagnostic Read or Write Data. AMD Geode™ LX Processors Data Book DC_CFIFO_DIAG Register Map CFIFO_DATA DC_CFIFO_DIAG Bit Descriptions 33234H...
Page 338 14 bits of accuracy in the hardware. The equation could be modified to allow for higher bits in the future by changing the 14-bit and 18-bit shift values. The only requirement is that the sum of the shift values be 32. DC_VID_DS_DELTA Register Map RSVD RSVD DC_VID_DS_DELTA Bit Descriptions Display Controller Register Descriptions VSYNC_SHIFT AMD Geode™ LX Processors Data Book...
Page 339 RAM. When programming the value in this field, software must calculate the sum of the GLIU0_MEM_OFFSET (DC Memory Offset 084h[31:24] and the appropriate Physical- to-Device descriptor(s) in GLIU0. AMD Geode™ LX Processors Data Book DC_GLIU0_MEM_OFFSET Register Map RSVD DC_DV_CTL Register Map...
Page 340 RAM. Reads will return the value of the “dirty” entry. The DV RAM Address is determined by the value in DV_RAM_AD (DC Memory Offset 084h[10:0]). DV_CTL Bit Descriptions (Continued) DC_DV_ACCESS Register Map RSVD DC_DV_ACCESS Bit Descriptions Display Controller Register Descriptions AMD Geode™ LX Processors Data Book...
Page 341 The value in this field must never exceed 8000h, which represents a 2:1 horizontal down- scale. If the width of the source image is greater than 1024 pixels, scaling is not sup- ported. AMD Geode™ LX Processors Data Book DC_GFX_SCALE Register Map DC_GFX_SCALE Bit Descriptions...
Page 342 Setting this bit to 1 enables the graphics scaler filter; This filter is provided to support scaling and interlacing of graphics data. DC_IRQ_FILT_CTL Register Map DC_IRQ_FILT_CTL Bit Descriptions Display Controller Register Descriptions RSVD FILT_ADDR AMD Geode™ LX Processors Data Book...
Page 343 TAP1 Tap 1 Coefficient. This coefficient is used for the first tap in the filter (the upper tap of the vertical filter or the leftmost tap of the horizontal filter). AMD Geode™ LX Processors Data Book DC_FILT_COEFF1 Register Map TAP2...
Page 344 VBI Upscale. When set, the VBI data is upscaled by 2. This is accomplished by repeat- ing data twice. DC_FILT_COEFF2 Register Map TAP5 DC_FILT_COEFF2 Bit Descriptions DC_VBI_EVEN_CTL Register Map VBI_EVEN_OFFSET DC_VBI_EVEN_CTL Bit Descriptions Display Controller Register Descriptions TAP4 AMD Geode™ LX Processors Data Book...
Page 345 15:12 RSVD Reserved. Set to 0. 11:0 VBI_H_START VBI Horizontal Start. Specifies the horizontal start position for VBI data minus 1 pixel. AMD Geode™ LX Processors Data Book DC_VBI_ODD_CTL Register Map VBI_ODD_OFFSET DC_VBI_ODD_CTL Bit Descriptions DC_VBI_HOR Register Map RSVD DC_VBI_HOR Bit Descriptions...
Page 346 This field is used for all frames if interlacing is disabled. RSVD Reserved. Set to 0. DC_VBI_LN_ODD Register Map LN_EN_ODD DC_VBI_LN_ODD Bit Descriptions DC_VBI_LN_EVEN Register Map LN_EN_EVEN DC_VBI_LN_EVEN Bit Descriptions Display Controller Register Descriptions RSVD RSVD AMD Geode™ LX Processors Data Book...
Page 347 23:0 CLR_KEY Color Key. This field represents the RGB value that will be compared to DC pixels when performing color key detection. AMD Geode™ LX Processors Data Book DC_VBI_PITCH Register Map VBI_Size DC_VBI_PITCH Bit Descriptions Register Map...
Page 348 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD CLR_KEY_Y_END DC_CLR_KEY_MASK Register Map CLR_KEY_MASK DC_CLR_KEY_MASK Bit Descriptions DC_CLR_KEY_X Register Map RSVD DC_CLR_KEY_X Bit Descriptions DC_CLR_KEY_Y Register Map RSVD Display Controller Register Descriptions CLR_KEY_X_START CLR_KEY_Y_START AMD Geode™ LX Processors Data Book...
Page 349 DC_IRQ_FILT_CTL (DC Memory Offset 094h). Clearing this bit disables interrupt gener- ation, but will NOT prevent IRQ, bit 16, from being set. AMD Geode™ LX Processors Data Book DC_CLR_KEY_Y Bit Descriptions DC_IRQ Register Map...
Page 350 VIP and that the skew counter is running. This bit is set when the VIP_VSYNC input is set and cleared when the skew counter expires. DC_GENLK_CTL Register Map DC_GENLK_CTL Bit Descriptions Display Controller Register Descriptions GENLK_SKW AMD Geode™ LX Processors Data Book...
Page 351 Y, U and V data. If YUV 4:2:0 is selected (DC Memory Offset 004h[20] = 1), the Video Y Buffer is used to hold only Y data while U and V data are stored in separate buffers. AMD Geode™ LX Processors Data Book 33234H OFFSET...
Page 352 YUV 4:2:0 is selected (DC Memory Offset 004h[20] = 1). The lower five bits should always be programmed as zero so that the start offset is aligned to a 32-byte boundary. Display Controller Register Descriptions OFFSET OFFSET AMD Geode™ LX Processors Data Book...
Page 353 FB_ACTIVE (DC Memory Offset 5Ch) is used to program the horizontal and vertical active values in the frame buffer when graphics scaling is enabled. AMD Geode™ LX Processors Data Book RSVD V_ADJUST = (V_PANEL - V_ACTIVE) / 2...
Page 354 Display Controller Register Descriptions RSVD V_BLANK_START RSVD V_SYNC_START AMD Geode™ LX Processors Data Book...
Page 355 ISR1). CRTCIO_SMI CRTC Register SMI. If = 1, an SMI was generated due to an I/O read or write to an non- implemented CRTC register. AMD Geode™ LX Processors Data Book VGA_CONFIG Register Map RSVD VGA_CONFIG Bit Descriptions VGA_STATUS Register Map...
Page 356 (Index 3?4h and 3?5h), Feature Control register (Index 3?Ah), and Input Status Register 1 (Index 3?Ah) as follows: ? = B when bit set to 0 (MDA I/O address emulation), ? = D when bit set to 1 (CGA address emulation). Display Controller Register Descriptions AMD Geode™ LX Processors Data Book...
Page 357 Reads as a 1 when either display enable signal is inactive. 6.6.17.4 VGA Feature Control Read Address 3CAh Write Address 3BAh or 3DAh Type Reset Value VGA Feature Control Register Bit Descriptions Name Description RSVD Reserved. AMD Geode™ LX Processors Data Book 33234H...
Page 358: Table 6-51. Vga Sequencer Registers Summary
I/O and memory accesses. VGA Reset Register Bit Descriptions Display Controller Register Descriptions Reset Value Reference Page 358 Page 358 Page 358 Page 359 Page 359 Page 360 Page 360 AMD Geode™ LX Processors Data Book...
Page 359 Reads to all maps are always enabled, and are unaffected by these bits. VGA Map Mask Register Bit Descriptions Name Description RSVD Reserved. Enable Map 3. Enable Map 2. Enable Map 1. Enable Map 0. AMD Geode™ LX Processors Data Book 33234H...
Page 360: Table 6-52. Font Table
(at least) 256 KB. RSVD Reserved. Display Controller Register Descriptions Table 6-52. Font Table Code AMD Geode™ LX Processors Data Book Font Table Location in Map 2 8 KB Block 1 8 KB Block 3 8 KB Block 5 8 KB Block 7...
Page 361: Table 6-53. Crtc Register Settings
Note: The Extended VGA Registers are accessed through the CRTC interface. This section only discusses the base VGA registers, however. See Section 6.6.23 "VGA Block Extended Registers" on page 384 for more information on the extended registers. AMD Geode™ LX Processors Data Book Table 6-53. CRTC Register Settings VGA Mode...
Page 362: Table 6-54. Crtc Registers Summary
Page 367 Page 367 Page 367 Page 367 Page 368 Page 368 Page 368 Page 369 Page 369 Page 369 Page 370 Page 370 Page 370 Page 372 Page 372 Page 372 Page 373 AMD Geode™ LX Processors Data Book...
Page 363 Horizontal Blank Start Register Bit Descriptions Name Description H_BLANK_ST Horizontal Blank Start. This value specifies the character position on the line where the horizontal blanking signal goes active. AMD Geode™ LX Processors Data Book CRTC Data Register Bit Descriptions 33234H...
Page 364 Horizontal Blank End bit 5. See H_BLANK_END[4:0] bit description (Index 03h[4:0]). RSVD Not Implemented. (HSync Delay). H_SYNC_END Horizontal Sync End. These bits represent the low five bits of the character position where the horizontal sync signal ends. Display Controller Register Descriptions AMD Geode™ LX Processors Data Book...
Page 365 Vertical Total Bit 8. See VTOTAL[7:0] bit description (Index 06h[7:0]). V_TOTAL9 is located at bit 5. 6.6.19.11 Preset Row Scan Index Type Reset Value Preset Row Scan Register Bit Descriptions Name Description RSVD Reserved. AMD Geode™ LX Processors Data Book Vertical Total Register Bit Descriptions Overflow Register Bit Descriptions 33234H...
Page 366 If this value is greater than the Cursor End value (CURS_END, Index 0Bh[4:0]), then no cursor is displayed. If this value is equal to the CURS_END value, then the cursor occupies a single scan line. Cursor Start Register Bit Descriptions Display Controller Register Descriptions AMD Geode™ LX Processors Data Book...
Page 367 0Fh[7:0]), this value specifies the frame buffer address where the cursor is displayed in text mode. The cursor will appear at the character whose memory address corresponds to this value. AMD Geode™ LX Processors Data Book Cursor End Register Bit Descriptions 33234H...
Page 368 Vertical Sync End Register Bits [3:0]. This field represents the low four bits of a com- pare value that specifies which scan line that the vertical sync signal goes inactive. Display Controller Register Descriptions AMD Geode™ LX Processors Data Book...
Page 369 (Index 17h[6]). RSVD Not Implemented. (Count by 4) Underline Location. This field specifies the row scan value where the underline appears in the character box in text modes. AMD Geode™ LX Processors Data Book Offset Register Bit Descriptions 33234H...
Page 370 VCLK Select. This bit determines the clocking for the vertical portion of the CRTC. If this bit is 0, the horizontal sync signal clocks the vertical section. If this bit is 1, the horizontal sync divided by two clocks the vertical section. Display Controller Register Descriptions AMD Geode™ LX Processors Data Book...
Page 371: Table 6-55. Crtc Memory Addressing Modes
Table 6-55. CRTC Memory Addressing Modes Frame Buffer Memory Address Bit MA10 MA11 MA12 MA13 MA14 MA15 AMD Geode™ LX Processors Data Book Byte Mode (01) Word Mode (00) A15 or A13 A13 or RS0 A12 or RS0 A14 or RS1 A13 or RS1...
Page 372 When this bit is 0, the next write to Index 3C0h will write an index value; when this bit is 1, the next write to Index 3C0h will write a data register value. RSVD Reserved. Line Compare Register Bit Descriptions Display Controller Register Descriptions AMD Geode™ LX Processors Data Book...
Page 373: Table 6-56. Graphics Controller Registers Summary
3CEh Type Reset Value VGA Graphics Controller Index Register Bit Descriptions Name Description RSVD Reserved. INDEX Index. AMD Geode™ LX Processors Data Book 33234H Reset Value Reference Page 373 Page 374 Page 374 Page 374 Page 375 Page 375 Page 376...
Page 374 VGA Enable Set/Reset Register Bit Descriptions Name Description RSVD Reserved. EN_SR_MP3 Enable Set/Reset Map 3. EN_SR_MP2 Enable Set/Reset Map 2. EN_SR_MP1 Enable Set/Reset Map 1. EN_SR_MP0 Enable Set/Reset Map 0. Display Controller Register Descriptions AMD Geode™ LX Processors Data Book...
Page 375 0 and 3. The CPU data byte written is rotated right, with low bits wrapping to the high bit positions. See the description of write modes (Section 6.5.5.3 on page 290) for more information. AMD Geode™ LX Processors Data Book 33234H...
Page 376 CPU read data contain a 1 in each pixel position where the color compare operation was true, and a 0 where the operation was false. When this bit is 0, frame buffer map data is returned. RSVD Reserved. Display Controller Register Descriptions AMD Geode™ LX Processors Data Book...
Page 377 Odd maps are then selected when CPU A0 = 1, and even maps selected when CPU A0 = 0. GPH_MD Graphics Mode. 0: Text mode operation. 1: Graphics mode operation. AMD Geode™ LX Processors Data Book 33234H...
Page 378: Table 6-57. Attribute Controller Registers Summary
Color Plane Enable Horizontal Pel Panning Color Select VGA Bit Mask Register Bit Descriptions Display Controller Register Descriptions Reset Value Reference Page 379 Page 379 Page 380 Page 380 Page 381 Page 381 Page 382 AMD Geode™ LX Processors Data Book...
Page 379 EGA palette is “programmed out of the way” in 256 color mode. These registers can only be read or written when the Internal Palette Address bit in the Index register (3C0h) is 0. AMD Geode™ LX Processors Data Book EGA Palette Register Bit Descriptions...
Page 380 Overscan Color Register Bit Descriptions Name Description OVER_COLOR Overscan Color. This value is output as the pixel value to the video DAC when the Dis- play Enable signal from the CRTC is inactive. Display Controller Register Descriptions AMD Geode™ LX Processors Data Book...
Page 381 Horizontal Pel Panning Register Bit Descriptions Name Description RSVD Reserved. Horizontal Pel Panning: This field specifies how many pixels the screen image should be shifted to the left by. AMD Geode™ LX Processors Data Book Bits [3:0] Mode 13h Panning 0000 0001 0010...
Page 382: Table 6-58. Video Dac Registers Summary
Palette Address (Read Mode) 3C7h DAC State 3C9h Palette Data 3C6h Pel Mask Color Select Register Bit Descriptions Display Controller Register Descriptions Reset Value Reference Page 383 Page 383 Page 383 Page 380 Page 380 AMD Geode™ LX Processors Data Book...
Page 383 Color Component Value. This is a 6-bit color component value that drives the video DAC for the appropriate color component when the current palette write address is used to address the video DAC in the pixel stream. AMD Geode™ LX Processors Data Book 33234H...
Page 384: Table 6-59. Extended Registers Summary
Note 1. R/W when unlocked, RO otherwise (see Section 6.6.23.1 "ExtendedRegisterLock" for details). Display Controller Register Descriptions Reset Value Reference Page 385 Page 385 Page 385 Page 386 Page 386 Page 386 Page 387 Page 387 Page 387 AMD Geode™ LX Processors Data Book...
Page 385 Start Address Register Bits [21:16]. Start Address Register Bits [23:18]: These bits [21:16] extend the VGA start address to 24 bits. Bits [17:10] are in Start Address Hi (Index 0Ch), and bits [9:2] are in Start Address Lo (Index 0Ch). AMD Geode™ LX Processors Data Book 33234H...
Page 386 Hold Count. When set, prevents the blink counter from incrementing with each leading edge VSYNC. RSVD Reserved. BLNK_CNT Blink Count. The blink counter is loaded with this value while the Sequencer Reset reg- ister is in the reset state. Display Controller Register Descriptions AMD Geode™ LX Processors Data Book...
Page 387 Four successive reads or writes to the CRTC data register at this index will return or write bytes 0 (bits [7:0]), 1 (bits [15:8]), 2 (bits [23:16]), then 3 (bits [31:24]) in sequence. AMD Geode™ LX Processors Data Book BlinkCounter Register Bit Descriptions...
Page 388: Video Processor
— Horizontal Upscaler (Programmable up to x8) • Control Registers • Mixer/Blender — Color Space Converter (CSC) — Gamma RAM — Color Keys — Alpha Blender • CRT DACs • TFT Interface • Video Output Port AMD Geode™ LX Processors Data Book Video Processor...
Page 389: Figure 6-23. Video Processor Block Diagram
Graphics Data Interface Dot Clock Companion Device Bypass Pixel Data Pixel Cntl Figure 6-23. Video Processor Block Diagram AMD Geode™ LX Processors Data Book Video Processor Module Video Processor Video Formatter (YUV) Delay X and Y Scaler Mixer/Blender (Overly with...
Page 390: Figure 6-24. Video Processor Block Diagram
Line Buffer 4 (5x480x64 bit) (4:2:2 or 4:2:0) Mixer/Blender or YUV Color Space Converter, and Gamma RAM) Video Processor Vertical Horizontal Scale Scale 4 Parallel 4-tap Filter 4-tap filters YUV444 or RGB888 to CRT AMD Geode™ LX Processors Data Book...
Page 391 Bits [10:5]: Green Bits [4:0]: Blue This format can be used for a second graphics plane if video mixing is not used. AMD Geode™ LX Processors Data Book 33234H Four subformats can be selected via the VID_FMT bits (VP Memory Offset 000h[3:2]):...
Page 392: Figure 6-25. Downscaler Block Diagram
Offset 078h) selects the type of downscaling factor to be used. Note: There is no vertical downscaling in the Video Pro- cessor module. Bypass 4-Tap Horizontal Filtering Downscaler Downscale Factors Figure 6-25. Downscaler Block Diagram Video Processor To line buffers AMD Geode™ LX Processors Data Book...
Page 393: Figure 6-26. Linear Interpolation Calculation
24-bit RGB video data. i+1,j Figure 6-26. Linear Interpolation Calculation AMD Geode™ LX Processors Data Book Color space conversion equations are based on the BT.601-1 recommendation: Standard definition color space conversion equations are based on Microsoft’s recommendations as follows:...
Page 394 Fig- ure 6-28 on page 396 illustrates the logic used to determine how to implement the color key and alpha-blend- ing logic. AMD Geode™ LX Processors Data Book Video Processor...
Page 395: Figure 6-27. Mixer Block Diagram
Video HD/SD Cursor_Color_Key CUR_COLOR_MASK VID_CLR_KEY VID_CLR_MASK VSYNC 31:24 SAT_Scale_EN RGB to HSV Graphics Saturation Control AMD Geode™ LX Processors Data Book CSC_VIDEO bypass_stream Palette palette_stream Compare Compare Alpha Color Registers and Cursor Color Values SAT_Scale CSC_GFX Figure 6-27. Mixer Block Diagram...
Page 396: Figure 6-28. Color Key And Alpha-Blending Logic
Graphics [31:24] = 00h? Use graphics Use video value value for this pixel for this pixel Video Processor VG_CK = 1? video pixel matches chroma key? Use graphics value for this pixel AMD Geode™ LX Processors Data Book...
Page 397: Table 6-60. Truth Table For Alpha-Blending
RAM). 6.7.5.3 Video Processor Module Display Interface The Video Processor module connects directly to either the internal CRT DACs, or provides a standard digital TFT interface. AMD Geode™ LX Processors Data Book 33234H Graphics Data Per-pixel Video Data Match Graphics...
Page 398: Figure 6-29. Vop Internal Block Diagram
BT.656 mode supported • Support for VIP 2.0 NON_INT bit (REPEAT and EXT_FLAG not supported) • BT.601 mode supported • VBI data supported (no support for ancillary data) Generator Data Data Formatter AMD Geode™ LX Processors Data Book Video Processor...
Page 399: Figure 6-30. 525-Line Ntsc Video Window
HBLANK VBLANK Figure 6-31. HBLANK and VBLANK for Lines 20-262, 283-524 AMD Geode™ LX Processors Data Book VBLANK is a function of the vertical line number and the horizontal pixel position. Figures 6-30 to 6-34 show the for- mation of these signals using a 525-line NTSC video win- dow.
Page 400: Figure 6-32. Hblank And Vblank For Lines 263, 525
Pixel Position Line Number HBLANK VBLANK Figure 6-33. HBLANK and VBLANK for Lines 1-18, 264-281 Pixel Position Line Number HBLANK VBLANK Figure 6-34. HBLANK and VBLANK for Lines 19, 282 AMD Geode™ LX Processors Data Book Video Processor L# + 1...
Page 401: Table 6-61. Vop Mode
Y1’ = Y1, U1’ = U1, V1’ = V1 Y2’ = Y2 Y3’ = Y3, U3’ = U3, V3’ = V3 etc. AMD Geode™ LX Processors Data Book 33234H Mode 1: 4:2:2 Interspersed In this mode, adjacent pairs of U/V sample data are aver- aged, with the U/V samples coming from the same adja- cent sample sets.
Page 402: Table 6-62. Sav/Eav Sequence
T, F, and V bits. — Task bit is used to indicate VBI data within the video stream (T = 0 for VBI Data, T = 1 for active video). — P3-P0 are ignored. Video Processor AMD Geode™ LX Processors Data Book...
Page 403: Figure 6-35. Bt.656 8/16 Bit Line Data
Horizontal Blanking EAV Code vip_data[7:0] vip_data[15:8] Horizontal Blanking AMD Geode™ LX Processors Data Book — New Video Flags - The P Nibble is redefined as [NON_INT,REPEAT,Reserved,EXT_FLAG]. – NON_INT - 1 = non-interlaced source, 0 = inter- laced source. – REPEAT - 1 = repeat field in 3:2 pull-down, 0 = not a repeat field (tied to 0).
Page 404: Table 6-64. Sav Vip Flags
This occurs during 3:2 pull-down. This flag enables a VIP master to drop the repeat field in the weave mode. This bit is not supported in the AMD Geode™ LX proces- sor (tied to 0). RSVD Reserved. EXT_FLAG 0 indicates no extended flags.
Page 405: Figure 6-36. Flat Panel Display Controller Block Diagram
Pixel Data Pixel Control Figure 6-36. Flat Panel Display Controller Block Diagram AMD Geode™ LX Processors Data Book • 9+9 or 12+12-bit, and 24-bit 2 pixels per clock TFT panel support. • Programmable dither, up to 64 levels. 6.7.7.2 FP Architecture Overview...
Page 406: Table 6-66. Panel Output Signal Mapping
TFT timing signals such as HSYNC, VSYNC, and LDE. One pixel (or two pixels in 2 pix/clk mode) is shifted on every positive edge of the clock as long as DISP_ENA is active. 18-Bit 24-Bit AMD Geode™ LX Processors Data Book Video Processor 9+9-Bit 12+12-Bit...
Page 407 2x2 pixel square would appear to be half as bright as the brightest red. The drawback is that fine details and boundaries between regions of differing color intensities become slightly blurred. AMD Geode™ LX Processors Data Book 18-Bit 24-Bit HSYNC...
Page 408: Figure 6-37. Dithered 8X8 Pixel Pattern
1s to the dithering patterns for the 4-, 3-, 2-, and 1- bit dithering schemes. Video Processor 10000000 01000000 01000000 01000000 10000000 01000000 01000000 10000000 01000000 01000000 01000000 01000000 10000000 01000000 01000000 10000000 AMD Geode™ LX Processors Data Book...
Page 409: Figure 6-38. N-Bit Dithering Pattern Schemes
Y-Count [3:0] 4-Bit Scheme X-Count[3:0] 000 001 010 011 100 Y-Count [3:0] 2-Bit Scheme Figure 6-38. N-Bit Dithering Pattern Schemes AMD Geode™ LX Processors Data Book 101 110 Y-Count [3:0] 101 110 Y-Count [3:0] 33234H X-Count[3:0] 000 001 010 011 100...
Page 410: Table 6-67. Register Settings For Dither Enable/Disable Feature
Bypass FP FP Memory Offset 408h[30] is set to 1 Video Processor AMD Geode™ LX Processors Data Book...
Page 411: Table 6-68. Display Rgb Modes
TFT Online: Normal functional, TFT display. CRT Legacy RGB: Use companion device as off-chip display controller, graphics only for CRT. TFT Legacy RGB: Use the AMD Geode companion device as off-chip display controller, graphics only for CRT. CRT Debug: Normal functional, access to debug sig- nals.
Page 412: Video Processor Register Descriptions
00000000_00000000h Reset Value 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_000000xxh 00000000_00xxxxxxh 00000000_00000000h AMD Geode™ LX Processors Data Book Reference Page 415 Page 415 Page 417 Page 417 Page 418 Page 418 Reference Page 419 Page 420 Reference Page 421...
Page 413 Even Alpha Window 1 Y Position (A1YE) 148h Even Alpha Window 2 Y Position (A2YE) 150h Even Alpha Window 3 Y Position (A3YE) 158h-3FFh Reserved AMD Geode™ LX Processors Data Book 33234H Reset Value Reference 00000000_00000C00h Page 430 00000000_00000000h Page 431...
Page 414 Reference 00000000_00000000h Page 451 00000000_00000000h Page 453 00000000_00000002h Page 454 00000000_00000000h Page 456 00000000_00000000h Page 457 00000000_00000000h Page 458 00000000_00000000h Page 458 00000000_00000001h Page 459 00000000_00000000h Page 459 00000000_00000000h Page 461 xxxxxxxx_xxxxxxxxh Page 451 AMD Geode™ LX Processors Data Book...
Page 415 63:24 RSVD Reserved. Reads back as 0. 23:8 DEV_ID Device ID. Identifies device (13F0h). REV_ID Revision ID. Identifies device revision. See AMD Geode™ LX Processors Specification Update document for value. 6.8.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG) MSR Address 48002001h Type...
Page 416 Resets to CRT; software must change if a different mode is required. 000: CRT. 001: Flat Panel. 010: Reserved. 011: Reserved. 100: CRT Debug mode. 101: Reserved. 110: VOP. 111: DRGB. VP Priority Domain. Video Processor module assigned priority domain identifier. Video Processor Register Descriptions AMD Geode™ LX Processors Data Book...
Page 417 RSVD (RO) Reserved (Read Only). DF Error Mask. 0: Unmask the Error (i.e., error generation is enabled). 1: Mask the Error (i.e., error generation is disabled). AMD Geode™ LX Processors Data Book GLD_MSR_ERROR Register Map RSVD RSVD GLD_MSR_ERROR Bit Descriptions...
Page 418 GLD Diagnostic MSR (GLD_MSR_DIAG) MSR Address 48002005h Type Reset Value 00000002_00000000h This register is reserved for internal use by AMD and should not be written to. GLD_MSR_PM Register Map RSVD RSVD GLD_MSR_PM Bit Descriptions Video Processor Register Descriptions AMD Geode™ LX Processors Data Book...
Page 419 1: 24-bit data to CRT DAC = gfx_data[23:0] (raw input from Display Controller). 18:16 RSVD Reserved. Reserved for test purposes. Set to 000 for normal operation. 15:0 Spares. Read/write, no function. AMD Geode™ LX Processors Data Book MSR_DIAG_VP Register Map RSVD TSEL MSR_DIAG_VP Bit Descriptions 33234H...
Page 420 Bit 27: DF_DISP_EN Bit 26: DF_LDE Bit 25: DF_VSYNC Bit 24: DF_HSYNC Bits [23:0]: DF_DRGB[23:0] 0: Registered output. 1: Direct output. MSR_PADSEL Register Map RSVD DF_DRGB[23:0] MSR_PADSEL Bit Descriptions Video Processor Register Descriptions DF_DRGB[31:26] AMD Geode™ LX Processors Data Book...
Page 421 Video Line Size (in DWORDs). Represents the number of DWORDs that make up the horizontal size of the source video data. Spares. Bits are R/W but have not function. AMD Geode™ LX Processors Data Book VCFG Register Map RSVD INIT_RD_ADDR...
Page 422 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD VCFG Bit Descriptions (Continued) DCFG Register Map RSVD RSVD Video Processor Register Descriptions RSVD AMD Geode™ LX Processors Data Book...
Page 423 Spares. Bits are read/write, but have no function. DAC_BL_EN DAC Blank Enable. Controls blanking of the CRT DACs. 0: DACs are constantly blanked. 1: DACs are blanked normally (i.e., during horizontal and vertical blank). AMD Geode™ LX Processors Data Book DCFG Bit Descriptions 33234H...
Page 424 Value = Desired screen position + (H_TOTAL – H_SYNC_END) – 14. (Note 1) Note 1. H_TOTAL and H_SYNC_END are the values written in the Display Controller module registers. DCFG Bit Descriptions (Continued) VX Register Map RSVD RSVD VX Bit Descriptions Video Processor Register Descriptions VID_X_START AMD Geode™ LX Processors Data Book...
Page 425 This bit is typically set if during vertical downscale, the 2nd line buffer fill hasn’t started before the Dot display has started. This indicates an error in that the GLIU line buffer fill can’t keep up with the Dot clock display rate. AMD Geode™ LX Processors Data Book VY Register Map RSVD...
Page 426 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD Name Description 63:24 RSVD (RO) Reserved (Read Only). Reads back as 0. Video Processor Register Descriptions SCL Bit Descriptions VCK Register Map RSVD VID_CLR_KEY VCK Bit Descriptions AMD Geode™ LX Processors Data Book...
Page 427 It allows a range of values to be used as the color key. AMD Geode™ LX Processors Data Book VCK Bit Descriptions (Continued)
Page 428 When a read or write to the Gamma Correction RAM occurs, the previous output value is held for one additional DOTCLK period. This effect should go unnoticed during normal operation. Video Processor Register Descriptions PAL_ADDR AMD Geode™ LX Processors Data Book...
Page 429 RGB to HSV conversion of the graphics. After scaling the S value, the result is then converted to YUV format prior to blending with the video. This 8-bit value represents 256 equal steps between 0 and 1. AMD Geode™ LX Processors Data Book SLR Register Map RSVD...
Page 430 0: The stream selected by the Display Configuration (DCFG) register (VP Memory Offset 008h[21]) is passed through gamma correction RAM. 1: Both graphics and video bypass gamma correction RAM. Video Processor Register Descriptions MISC Register Map RSVD MISC Bit Descriptions AMD Geode™ LX Processors Data Book RSVD...
Page 431 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 X_ACC_INIT AMD Geode™ LX Processors Data Book VYS Register Map RSVD VYS Bit Descriptions If no scaling is intended, set to 10000h.
Page 432 If no scaling is intended, set to 10000h. Will be greater than 1000h when down- scaling. Will be less than 10000h when upscaling. VDC Register Map RSVD RSVD VDC Bit Descriptions Video Processor Register Descriptions AMD Geode™ LX Processors Data Book...
Page 433 CRC check status. In 32-bit CRC mode, the full 32-bit signature can be read from the 32- Bit CRC Signature (VP Memory Offset 090h[31:0]). Then proceed to reset SIGEN, which initializes SIGVAL as an essential preparation for the next round of CRC checks. AMD Geode™ LX Processors Data Book CRC Register Map RSVD...
Page 434 Priority is used to determine display order for overlapping alpha windows. This field is reset by hardware to 00. CRC32 Register Map RSVD SIG_VALUE CRC32 Bit Descriptions VDE Register Map RSVD VDE Bit Descriptions Video Processor Register Descriptions AMD Geode™ LX Processors Data Book...
Page 435 1: Enable. The video stream is passed through the CSC (for YUV to RGB conversion). HDSD High Definition/Standard Definition CSC. Determines which algorithm to use for graphics color space conversion from RGB to YUV. 0: Standard Definition. 1: High Definition. AMD Geode™ LX Processors Data Book VDE Bit Descriptions (Continued) 33234H...
Page 436 If a match is detected, the pixel is replaced by a 24-bit value from one of the cursor color registers. VDE Bit Descriptions (Continued) -> YUV -> YUV CCK Register Map RSVD CUR_COLOR_KEY CCK Bit Descriptions Video Processor Register Descriptions AMD Geode™ LX Processors Data Book...
Page 437 This is one of two possible cursor color values. Bits[28:24] of the Cursor Color Key regis- ter (VP Memory Offset 0A0h) determine a bit of the graphics data that if even, selects this color to be used. AMD Geode™ LX Processors Data Book CCM Register Map RSVD...
Page 438 The value of (H_TOTAL – H_SYNC_END) is sometimes referred to as “horizontal back porch.” Video Processor Register Descriptions CC2 Register Map RSVD CUR_COLOR_REG2 CC2 Bit Descriptions A1X Register Map RSVD RSVD A1X Bit Descriptions AMD Geode™ LX Processors Data Book ALPHA1_X_START...
Page 439 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD AMD Geode™ LX Processors Data Book A1Y Register Map RSVD...
Page 440 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD Video Processor Register Descriptions A1C Bit Descriptions A1T Register Map RSVD ALPHA1_INC AMD Geode™ LX Processors Data Book ALPHA1_MUL...
Page 441 Note 1. H_TOTAL and H_SYNC_END are values programmed in the Display Controller module registers. The value of (H_TOTAL – H_SYNC_END) is sometimes referred to as “horizontal back porch.” AMD Geode™ LX Processors Data Book A1T Bit Descriptions A2X Register Map...
Page 442 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD Video Processor Register Descriptions A2Y Register Map RSVD RSVD A2Y Bit Descriptions A2C Register Map RSVD ALPHA2_COLOR_REG AMD Geode™ LX Processors Data Book ALPHA2_Y_START...
Page 443 (bits [31:24] of the video data path) multiplied with the alpha multi- plier (ALPHA2_MUL, bits [7:0]) at the start of the next frame. This bit is cleared by the de- assertion of VSYNC. AMD Geode™ LX Processors Data Book A2C Bit Descriptions A2T Register Map...
Page 444 Note 1. H_TOTAL and H_SYNC_END are values programmed in the Display Controller module registers. The value of (H_TOTAL – H_SYNC_END) is sometimes referred to as “horizontal back porch.” A2T Bit Descriptions (Continued) A3X Register Map RSVD RSVD A3X Bit Descriptions Video Processor Register Descriptions ALPHA3_X_START AMD Geode™ LX Processors Data Book...
Page 445 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD AMD Geode™ LX Processors Data Book A3Y Register Map RSVD...
Page 446 (ALPHA3_MUL, bits [7:0]) at the start of the next frame. This bit is cleared by the de- assertion of VSYNC. Video Processor Register Descriptions A3C Bit Descriptions A3T Register Map RSVD ALPHA3_INC A3T Bit Descriptions AMD Geode™ LX Processors Data Book ALPHA3_MUL...
Page 447 15:11 RSVD (RO) Reserved (Read Only). Reads back as 0. 10:0 Video Y Request. Indicates the line number to start requesting video data from. AMD Geode™ LX Processors Data Book A3T Bit Descriptions (Continued) VRR Register Map RSVD RSVD VRR Bit Descriptions...
Page 448 Reserved (Read Only). Reads back as 0. RSVD Reserved. Reserved for test purposes. AWT Register Map RSVD AWT Bit Descriptions VTM Register Map RSVD RSVD VTM Bit Descriptions Video Processor Register Descriptions RSVD RSVD RSVD AMD Geode™ LX Processors Data Book...
Page 449 Value = Desired screen position + (V_TOTAL – V_SYNC_END) + 1. (Note 1) Note 1.V_TOTAL and V_SYNC_END are values programmed in the Display Controller module registers. The value of (V_TOTAL – V_SYNC_END) is sometimes referred to as “vertical back porch”. AMD Geode™ LX Processors Data Book VYE Register Map RSVD...
Page 450 Note 1. V_TOTAL and V_SYNC_END are values programmed in the Display Controller module registers. The value of (V_TOTAL – V_SYNC_END) is sometimes referred to as “vertical back porch”. Video Processor Register Descriptions A2YE Register Map RSVD RSVD A2YE Bit Descriptions A3YE Register Map RSVD RSVD A3YE Bit Descriptions AMD Geode™ LX Processors Data Book ALPHA2_Y_START ALPHA3_Y_START...
Page 451 Memory Offset 408h[23] controls the polarity of the output VSYNC. 0: FP_VSYNC is normally low, transitioning high during sync interval. (Default) 1: FP_VSYNC is normally high, transitioning low during sync interval AMD Geode™ LX Processors Data Book VCR Register Map VCR Bit Descriptions...
Page 452 HSYNC_SRC bit (bit 27) set to 0. (Default) 00001-11111: The HSYNC pulse width can be varied from one to 31 DOTCLKs. PT1 Bit Descriptions (Continued) Video Processor Register Descriptions AMD Geode™ LX Processors Data Book...
Page 453 VP Memory Offset 400h[29] selects the polarity of the input HSYNC, and this bit controls the output polarity. 0: HSYNC output is active high. 1: HSYNC output is active low 21:20 RSVD Reserved. These bits are not defined. AMD Geode™ LX Processors Data Book PT2 Register Map RSVD RSVD PIXF PT2 Bit Descriptions 33234H...
Page 454 The hardware will not function properly if this bit is set to 1. PT2 Bit Descriptions (Continued) SHFCLK = DOTCLK. SHFCLK = 1/2 of DOTCLK. PM Register Map RSVD HDEL VDEL PM Bit Descriptions Video Processor Register Descriptions AMD Geode™ LX Processors Data Book...
Page 455 Panel OFF Status (Read Only). A 1 indicates the flat panel is currently fully off. PANEL_ON (RO) Panel ON Status (Read Only). A 1 indicates the flat panel is currently fully on. AMD Geode™ LX Processors Data Book PM Bit Descriptions (Continued) CORE...
Page 456 011: Selects 3 bits as dither bits. 100: Selects 2 bits as dither bits. 101: Selects 1 bits as dither bits. 110, 111: Reserved. Video Processor Register Descriptions DFC Register Map RSVD DFC Bit Descriptions AMD Geode™ LX Processors Data Book RSVD...
Page 457 1, the RAM goes into power-down mode. ADDR RAM Address. This 6-bit field specifies the address to be used for the next access to the dither RAM. AMD Geode™ LX Processors Data Book DFC Bit Descriptions (Continued) DCA Register Map RSVD...
Page 458 Signature Enable. Enables/disables signature capture. 1: Enable signature capture. 0: Disable signature capture. DMD Register Map RSVD RDAT DMD Bit Descriptions CRC Register Map RSVD RSVD CRC Bit Descriptions Video Processor Register Descriptions FRCT AMD Geode™ LX Processors Data Book...
Page 459 Valid Signature (Read Only). If signature enabled, this bit can be read to determine if the signature is valid. INV DE POL Invert Display Enable Polarity. Set to 1 to invert polarity of display enable (for 601 mode only). AMD Geode™ LX Processors Data Book CRC32 Register Map RSVD CRC32 Bit Descriptions Register Map...
Page 460 CRC check status. Then proceed to reset the SIGE which initializes VP Memory Offset 808h[31:0] as an essential preparation for the next round of CRC checks. Video Processor Register Descriptions Bit Descriptions (Continued) AMD Geode™ LX Processors Data Book...
Page 461 Video Processor Register Descriptions VOP_CONFIG Name Description SC120X_MODE SC120X Compatible Mode. Creates EAV/SAV codes consistent with the AMD Geode™ SC1200 and SC1201 processor’s VOP. 0: Normal mode. 1: SC1200/SC1201 compatible mode. Set to 1 for BT.601 mode. 422_MODE 4:4:4 to 4:2:2 Conversion Algorithm. Selects which method is used to convert 4:4:4 data to 4:2:2.
Page 462: Video Input Port
Rotation/Bob A or B Standard Mode A or B Not Applicable A or B Rotation A or B SC1200 Compatible A or B VBI Data A or B Ancillary Data Message Data RAW Data AMD Geode™ LX Processors Data Book...
Page 463: Figure 6-39. Vip Block Diagram
Clock GLIU Clock Control VIPSYNC Planar mode: 512 byte(64 QWORDs) YUV, Ancillary FIFO Linear mode: 1536 byte(192 QWORDs) Video, 256 (64 QWORDs) byte Ancillary FIFO AMD Geode™ LX Processors Data Book Dual Port QWORD = 64 bits Capture RAM (256x64)
Page 464 6.9.2.5 GLIU Interface The GLIU provides a standard interface to the AMD Geode LX processor. The VIP is both a write master and a slave on this bus. As a write master, the VIP performs write requests to send single beat writes, or a burst of four QWORDs to memory.
Page 465 8-bit streaming data, allowing the AMD Geode CS5536 companion device connected to the VIP to load data directly into the AMD Geode LX proces- sor’s system memory. The Message Passing and Data Streaming modes are not defined in the VESA 2.0 specifi- cation.
Page 466: Table 6-73. Sav/Eav Sequence
(This function needs to be enabled in VIP Memory Offset 04h[29]). – EXT_FLAG: 1 = Extra flag byte follows this EAV, 0 = no extra flag byte (not implemented). Video Input Port AMD Geode™ LX Processors Data Book...
Page 467: Figure 6-40. Bt.656, 8/16-Bit Line Data
EAV Code VIP_DATA[7:0] VIP_DATA[15:8] AMD Geode™ LX Processors Data Book repeat flag is set during 3:2 pull down. In 3:2 pull down, fields are repeated to increase the frame rate. The VIP ignores fields (lines) with the repeat flag set. This reducers the amount of data being transferred to system memory, reducing overall bandwidth requirements.
Page 468: Figure 6-41. 525 Line, 60 Hz Digital Vertical Timing
Line 20(V = 0) 4-19 20-263 264-265 266-282 Line 264 (V = 1) 283-525 Line 283 (V = 0) Line 525 (V = 0) Line 1 (V = 1) AMD Geode™ LX Processors Data Book Video Input Port (EAV) (SAV)
Page 469: Figure 6-42. Ancillary Data Packets
VID[7:0] 6 Byte Ancillary Header VID[15:8] AMD Geode™ LX Processors Data Book explanation. There is no restriction on the code in the data section of the packet (codes 00 and FF are allowed) The SAV/EAV packet preamble detection circuitry is disabled during the reception of these NN blocks of data to allow reception of 00, FF codes.
Page 470: Figure 6-43. Message Passing Data Packet
Message Passing Mode The Message Passing mode (MSG) allows an external device to pass raw data packets to the AMD Geode LX pro- cessor system memory (see Figure 6-43). In Message Passing mode, VID8 is redefined as a start message indi- cation and VID9 is redefined as an end message indica- tion.
Page 471: Figure 6-45. Bt.601 Mode Default Field Detection
Even field is indicated when leading edge of VSYNC occurs prior to the leading edge of HSYNC. Figure 6-45. BT.601 Mode Default Field Detection AMD Geode™ LX Processors Data Book within the window, the field is odd. If the leading edge of VSYNC occurs outside the window, the field is even.
Page 472: Figure 6-46. Bt.601 Mode Programmable Field Detection
Figure 6-47. BT.601 Mode Horizontal Timing line #1 field_detect_duration odd field even field line #1 field_detect_duration odd field even field video data 10 11 D2 D3 D4 D5 D6 A = 3 B = 12 Video Input Port AMD Geode™ LX Processors Data Book...
Page 473: Figure 6-48. Bt.601 Mode Vertical Timing
Weave. Two sets of buffers (six buffers) are used to store the odd and even field data separately when using the Bob method of de-interlacing. AMD Geode™ LX Processors Data Book VBI Data Video Data C = 4...
Page 474: Figure 6-49. Yuv 4:2:2 To Yuv 4:2:0 Translation
Interlaced (Weave) - Discard even line UV values in both input fields Y SAMPLE CB,CR SAMPLE Figure 6-49. YUV 4:2:2 to YUV 4:2:0 Translation (single frame buffer in system memory) (single frame buffer in system memory) Video Input Port YUV 4:2:0 YUV 4:2:0 YUV 4:2:0 AMD Geode™ LX Processors Data Book...
Page 475: Table 6-74. Vip Data Types / Memory Registers
Message passing STRM Data Streaming AMD Geode™ LX Processors Data Book MSG and STRM modes are proprietary data transfer for- mats and are not defined in the VESA VIP specification. Table 6-74 defines the data types received in each mode.
Page 476: Figure 6-50. Dual Buffer For Message Passing And Data Streaming Modes
6.9.10.4 Message Passing/Data Streaming Modes The MSG and STRM modes provide a mechanism for the AMD Geode CS5536 companion device to send raw data to the AMD Geode LX processor system memory. MSG and STRM modes have identical software models. Two...
Page 477: Figure 6-51. Example Vip Yuv 4:2:2 Sav/Eav Packets Stored In System Memory In A Linear Buffer
Task A odd VBI data, Task A even VBI data, Task B odd VBI data, Task B even VBI data Figure 6-51. Example VIP YUV 4:2:2 SAV/EAV Packets Stored in System Memory in a Linear Buffer AMD Geode™ LX Processors Data Book line 1 start...
Page 478: Figure 6-52. Example Vip Yuv 4:2:0 Planar Buffer
#1 Y values Y Buffer line #1 U values U pitch = task_A_U_pitch U Buffer (all base registers are 8-byte aligned) line #1 V values V pitch = task_A_V_pitch V Buffer task_A_UV_pitch Video Input Port AMD Geode™ LX Processors Data Book...
Page 479: Figure 6-53. Example Vip 8/16- And 10-Bit Ancillary Packets Stored In System Memory
10-BIT ANCILLARY DATA Figure 6-53. Example VIP 8/16- and 10-bit Ancillary Packets Stored in System Memory AMD Geode™ LX Processors Data Book packet 1 start - buffer start data NN=4 SDID data data data...
Page 480 VIP Memory Offset 00h[23] (ERR_DETECT) must be set to 1 to enable the runaway line error. A runaway line error causes video reception to stop. Video reception starts again at the beginning of the next line. AMD Geode™ LX Processors Data Book Video Input Port...
Page 481 (for interlaced video data only). Current Line = VIP Line Target - Indicates that the video line number programmed in the VIP Current/Target register (VIP Memory Offset 10h) has been reached. AMD Geode™ LX Processors Data Book 33234H 6.9.13 VIP Input Video Status The VIP checks the input video for conditions that could indicate an invalid data stream.
Page 482: Video Input Port Register Descriptions
FFFFFFFFh 00000000h 00000000h 00000000h 00000000h 00000000h 00000020h 00000000h 00000000h 00000000h 00000000h 00000000h AMD Geode™ LX Processors Data Book Reference Page 484 Page 484 Page 485 Page 486 Page 487 Page 487 Reference Page 488 Page 490 Page 492 Page 494...
Page 483 VIP FIFO Address (VIP_FIFO_R_W_ADDR) VIP FIFO Data (VIP_FIFO_DATA) VIP VSYNC Error Count (VIP_SYNC_ERR_COUNT) VIP Task A U Even Offset (VIP_TASK_A_U_EVEN_OFFSET) VIP Task A V Even Offset (VIP_TASK_A_V_EVEN_OFFSET) AMD Geode™ LX Processors Data Book 33234H Reset Value Reference 00000000h Page 502 00000000h...
Page 484 Number of Clock Domains. The VIP contains two clock domains; GLIU clock and VIP video clock. 23:8 DEV_ID Device ID. Identifies device (03C4h). REV_ID Revision ID. Identifies device revision. See AMD Geode™ LX Processors Specification Update document for value. 6.10.1.2 GLD Configuration MSR (GLD_MSR_CONFIG) MSR Address 54002001h Type...
Page 485 Bit 3: Start of even field. Bit 2: Start of odd field. Bit 1: Current line = VIP Line Target (see Current/Target Line register). Bit 0: GLIU Address or Type error. AMD Geode™ LX Processors Data Book GLD_MSR_SMI Register Map RSVD GLD_MSR_SMI Bit Descriptions...
Page 486 0: Unmask the error (Enabled). 1: Mask the error (Disabled). Error Mask 0. 0: Unmask the error (Enabled). 1: Mask the error (Disabled). GLD_MSR_ERROR Register Map RSVD E1 E0 GLD_MSR_ERROR Bit Descriptions Video Input Port Register Descriptions RSVD AMD Geode™ LX Processors Data Book...
Page 487 6.10.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG) MSR Address 54002005h Type Reset Value 000000000_ 00000000h This register is reserved for internal use by AMD and should not be written to. AMD Geode™ LX Processors Data Book GLD_MSR_PM Register Map RSVD RSVD GLD_MSR_PM Bit Descriptions...
Page 488 Bit 21: Number of clocks per active line error (checks that each line has the same # of data). Bit 20: Loss of VIP clock (watchdog timer using GLIU clocks --128 GLIU clocks). VIP_CTL_REG1 Register Map DT_EN VIP_CTL_REG1 Bit Descriptions Video Input Port Register Descriptions RUN_MODE P VIP_MODE AMD Geode™ LX Processors Data Book...
Page 489 111: Start capture (required for msg/data streaming modes). Planar. Determines if video data is stored in a linear format or planar format in system memory. 0: Store data in linear format. 1: Store video data in planar format. AMD Geode™ LX Processors Data Book 33234H...
Page 490 10-bit Ancillary Data Input. When set to 1, ancillary data is received as 10-bit data. (This is only applicable in 16-bit VIP mode). VIP_CTL_REG2 Register Map VIP_CTL_REG2 Bit Descriptions Video Input Port Register Descriptions AMD Geode™ LX Processors Data Book...
Page 491 VSYNC Select. Selects signal timing for VIP_VSYNC output to the DC. 000: Sync from pin. 001: Inverted sync from pin. 010: VBLANK. 011: Inverted VBLANK. 100: Field. 101: Inverted field. 110: When vip_current_line = target_line. 111: 0. AMD Geode™ LX Processors Data Book 33234H...
Page 492 RSVD Reserved. VIP_STATUS Register Map VIP_STATUS Bit Descriptions The following base registers are updated at a start-of-frame event. Video Input Port Register Descriptions RSVD RSVD AMD Geode™ LX Processors Data Book...
Page 493 Writing a 1 to a bit resets it to 0. These bits are enabled when the corresponding DT_EN bits are set in the VIP Control 1 register (VIP Memory Offset 00h) along with the VIP_MODE bits. AMD Geode™ LX Processors Data Book 33234H...
Page 494 Bit 1: When enabled (0), allows current line = VIP Line Target INT (see Current/Target Line register). Bit 0: Not used (R/W). VIP_INT Register Map VIP_INT Bit Descriptions Video Input Port Register Descriptions INT_MASK AMD Geode™ LX Processors Data Book...
Page 495 (1536 bytes) can be written past this address (max # data in FIFO, although it is more likely that ~10-20 QWORDs are written. RSVD Reserved. Set to 0. AMD Geode™ LX Processors Data Book VIP_CUR_TAR Register Map VIP_MAX_ADDR Register Map MAX_ADDR...
Page 496 Base Register Not Updated bit is cleared. Video Input Port Register Descriptions Program to 00000 Program to 00000 AMD Geode™ LX Processors Data Book...
Page 497 32-byte aligned. (Bits [4:0] are required to be 00000.) Note: AMD Geode™ LX Processors Data Book This register is double buffered. When a new value is written to this register, the new value is placed in a special pending register, and the Base Register Not Updated bit (VIP Memory Offset 08h[16]) is set to 1.
Page 498 It is then up to the software to do a FIFO reset to recover from the overflow condition VIP_TASK_A_VID_PITCH Register Map Program to 00000 TASK_A_VIDEO_PITCH VIP_CONTRL_REG3 Register Map RSVD VIP_CONTRL_REG3 Bit Descriptions Video Input Port Register Descriptions Program to 00000 RSVD AMD Geode™ LX Processors Data Book...
Page 499 This value must be 32-byte aligned. (Bits [4:0] are required to be 00000.) AMD Geode™ LX Processors Data Book The DD bit (VIP Memory Offset 00h[16]) should be set to 1 or even lines will also be decimated.
Page 500 Base Register Not Updated bit is cleared. Video Input Port Register Descriptions Program to 00000 AMD Geode™ LX Processors Data Book...
Page 501 00000.) Note: AMD Geode™ LX Processors Data Book This register is double buffered. When a new value is written to this register, the new value is placed in a special pending register, and the “Base Register Not Updated”...
Page 502 When the first data of the next field is cap- tured, the pending values of all base registers are written to the appropriate base registers, and the VBI Base Register Not Updated bit is cleared. TASK_B_DATA_PITCH_VERT_START_EVEN Video Input Port Register Descriptions AMD Geode™ LX Processors Data Book...
Page 503 NI bit in (VIP Memory Offset 00h[19]) is set (non-interlaced mode), all frames are considered to be odd fields. AMD Geode™ LX Processors Data Book TASK_B_V_OFFSET_START_ODD This register in NOT double buffered and should be initialized before start of video capture.
Page 504 This register in NOT double buffered and should be initialized before start of video capture. VIP_ANC_MSG_1_BASE Register Map ANC_MSG_1_BASE This register is NOT double buffered. Video Input Port Register Descriptions Program to 00000 Program to 00000 AMD Geode™ LX Processors Data Book...
Page 505 Changes to this register take effect immediately (not double buffered). The value in this register is 8-byte aligned. Bits [2:0] are ignored. AMD Geode™ LX Processors Data Book VIP_ANC_MSG_2_BASE Register Map ANC_MSG_2_BASE This register is NOT double buffered.
Page 506 BT.601 non-interlaced modes, this register determines when the video capture starts. See Figure 6-48 "BT.601 Mode Vertical Timing" on page 473 for additional detail. VIP_PAGE_OFFSET Register Map PAGE_OFFSET VIP_PAGE_OFFSET Bit Descriptions RSVD Video Input Port Register Descriptions Program to 00000 VERT_START AMD Geode™ LX Processors Data Book...
Page 507 FIFO_ADDR (VIP Memory Offset 70h[7:0]). When the FF_R/W bit is reset, data from the FIFO corresponding to the address in the FIFO_ADDR is returned AMD Geode™ LX Processors Data Book VIP_FIFO_R_W_ADDR Register Map RSVD VIP_FIFO_R_W_ADDR Bit Descriptions...
Page 508 32-byte aligned. (Bits [4:0] are required to be 00000.) VIP_SYNC_ERR_COUNT Register Map VERTICAL_COUNT A 60 Hz VBLANK rate @75 MHz input clock = 1,250,000 clocks. TASK_A_U_EVEN_OFFSET Video Input Port Register Descriptions Program to 00000 AMD Geode™ LX Processors Data Book...
Page 509 This reg- ister is not used when in non-interlaced input mode. The value in this register needs to be 32-byte aligned. (Bits [4:0] are required to be 00000.) AMD Geode™ LX Processors Data Book TASK_A_V_EVEN_OFFSET 33234H...
Page 510: Security Block
— > 40 MB/Sec. encrypt or decrypt Security Block AES Engine Clock Control Unit SB Specific Registers Clock Control Unit EEPROM ID Interface True Random Number Generator Figure 6-54. Security Block Diagram Security Block EEPROM AMD Geode™ LX Processors Data Book...
Page 511 6.11.2 Functional Description The AES engine provides ECB and CBC 128-bit hardware encryption and decryption for the AMD Geode LX proces- sor using the Advanced Encryption Standard algorithm. The Security Block has two key sources. One is a hidden 128-bit key stored in non-volatile memory. It is expected...
Page 512: Table 6-77. Eeprom Address Map
The mask bits may be used to enable either an inter- rupt or an SMI if desired. 6.11.2.3 GLIU Interface The GLIU provides a standard interface to the AMD Geode LX processor. The Security Block is both a master and a slave on this bus.
Page 513: Security Block Register Descriptions
SB CBC Initialization Vector 0 (SB_CBC_IV_0) 044h SB CBC Initialization Vector 1 (SB_CBC_IV_1) AMD Geode™ LX Processors Data Book 33234H tables that include reset values and page references where the bit descriptions are provided. The MSR address is derived from the perspective of the CPU Core.
Page 514 SB EEPROM Security State (SB_EEPROM_SEC_STATE) Security Block Register Descriptions Reset Value Reference 00000000h Page 528 00000000h Page 528 00000000h Page 529 00000001h Page 529 00000000h Page 530 000000FFh Page 531 00000000h Page 531 00000000h Page 532 AMD Geode™ LX Processors Data Book...
Page 515 Description 63:24 RSVD Reserved. 23:8 DEV_ID Device ID. Identifies device (1304h). REV_ID Revision ID. Identifies device revision. See AMD Geode™ LX Processors Specification Update document for value. 6.12.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG) MSR Address 58002001h Type Reset Value 00000000_00000000h...
Page 516 Bit 0: When enabled (0), allows AES Context A Complete SMI. 6.12.1.4 GLD Error MSR (GLD_MSR_ERROR) MSR Address 58002003h Type Reset Value 00000000_00000019h GLD_MSR_SMI Register Map RSVD RSVD GLD_MSR_SMI Bit Descriptions Security Block Register Descriptions SMI_STAT SMI_MASK AMD Geode™ LX Processors Data Book...
Page 517 Response A Error will generate an error. RSVD Reserved. AES_ERR_ AES Error Mask. Reserved Type. MASK 0: Unmask the Error (enabled). 1: Mask the Error (disabled). AMD Geode™ LX Processors Data Book GLD_MSR_ERROR Register Map RSVD RSVD GLD_MSR_Error Bit Descriptions 33234H RSVD RSVD...
Page 518 6.12.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG) MSR Address 58002005h Type Reset Value 00000000_00000000h This register is reserved for internal use by AMD and should not be written to. GLD_MSR_PM Register Map RSVD RSVD GLD_MSR_PM Bit Descriptions Security Block Register Descriptions AMD Geode™ LX Processors Data Book...
Page 519 AES registers, (including the writable key), nor does it affect EEPROM operations. When this bit is cleared, the DMA operations read and write bytes with the same byte order as they appear in memory. AMD Geode™ LX Processors Data Book GLD_MSR_CTRL Register Map RSVD...
Page 520 Encrypt for A Pointer. When set, the AES operates in encryption mode. When reset, it operates in decryption mode. SB_CTL_A Register Map RSVD SB_CTL_A Register Bit Descriptions Security Block Register Descriptions RSVD AMD Geode™ LX Processors Data Book...
Page 521 A pointer set is already underway, the new operation for pointer set B will not start until the previous A operation completes. If both A and B start bits are asserted in the same write operation, the A operation take precedence. AMD Geode™ LX Processors Data Book SB_CTL_B Register Map RSVD...
Page 522 Memory Offset 004h[0] = 1). RSVD Reserved. Set to 0. SB_AES_INT Register Map 16 15 14 13 12 11 10 INT_STATUS SB_AES_INT Register Bit Descriptions SB_SOURCE_A Register Map SOURCE_A Security Block Register Descriptions RSVD INT_MASK RSVD AMD Geode™ LX Processors Data Book...
Page 523 SB Memory Offset 000h[0] = 1). This register can be modified during an operation using the B pointer set (while STB is asserted, SB Memory Offset 004h[0] = 1). RSVD Reserved. AMD Geode™ LX Processors Data Book SB_DEST_A Register Map Destination A SB_DEST_A Register Bit Descriptions...
Page 524 B pointer set (while STB is asserted, SB Memory Offset 004h[0] = 1). RSVD Reserved. Set to 0. SB_SOURCE_B Register Map SOURCE_B SB_DEST_B Register Map DEST_B SB_DEST_B Register Bit Descriptions Security Block Register Descriptions RSVD RSVD AMD Geode™ LX Processors Data Book...
Page 525 AES encryption or decryption operation. To prevent one process from reading the key written by another process, this register is not read- able. AMD Geode™ LX Processors Data Book SB_LENGTH_B Register Map LENGTH_B Register Map...
Page 526 SB_WKEY_1 Register Map WKEY_1[63:32] SB_WKEY_1 Bit Descriptions SB_WKEY_2 Register Map WKEY_2[95:64] SB_WKEY_2 Bit Descriptions Security Block Register Descriptions AMD Geode™ LX Processors Data Book...
Page 527 IDLE. (A and B start bits, SB Memory Offset 000h and 004h, bit 0 = 0). This reg- ister must be programmed with the IV vector prior to starting an AES CBC mode encryption or decryption. AMD Geode™ LX Processors Data Book SB_WKEY_3 Register Map WKEY_3[127:96]...
Page 528 SB Memory Offset 000h and 004h, bit 0 = 0). This register must be pro- grammed with the IV prior to starting an AES CBC mode encryption or decryption. SB_CBC_IV_3 Register Map CBC_IV_3[127:96] (rev2.0) SB_CBC_IV_3 Bit Descriptions Security Block Register Descriptions AMD Geode™ LX Processors Data Book...
Page 529 Reserved. Returns 0. TRNG_VALID Random Number Valid. When 1, the random number is valid. When 0, the random number is in the process of being generated. AMD Geode™ LX Processors Data Book SB_RANDOM_NUM Register Map RANDOM_NUM SB Random Number Bit Descriptions...
Page 530 EEPROM Complete flag in the AES Interrupt register (SB Memory Offset 008h[18]) and in the SMI MSR register (MSR 58002002h[34]). SB_EEPROM_COMM Register Map RSVD SB_EEPROM_COMM Bit Descriptions Security Block Register Descriptions RSVD AMD Geode™ LX Processors Data Book...
Page 531 Note that when reading a hidden location, this register will return the previous read or write data with no indication of an error. Writes to locked locations are ignored with no indication of an error. AMD Geode™ LX Processors Data Book SB_EEPROM_ADDR Register Map RSVD...
Page 532 Debug Lock. This register holds the 3-bit value of the access control bits used to dis- able certain debug features of the AMD Geode LX processor. If any of these bits are reset, debug operations are blocked. These bits correspond to the state of bits [2:0] of byte 1 of the EEPROM array as read after the last reset.
Page 533: Geodelink™ Control Processor
• Internal logic analyzer/debugger • 1KB FIFO/SRAM • Compliant with GLIU System Architecture Specification v1.07 • Supports AMD Geode™ CS5536 companion device interface • Supports physical pins for SUSPA# and IRQ13 • Supports muxed pin for SUSP# Scan, BIST, Clock, Reset, Suspend Signals TCLK IEEE 1149.1...
Page 534: Table 6-81. Tap Control Instructions (25-Bit Ir)
BYPASS Name Description TAPSCAN# Also USER[6] in the design. This is a user bit added by AMD; low indicates that an inter- nal scan chain is accessed by the TAP. 23:18 USER[5:0] User bits used to identify an internal scan chain or, if bit 24 is high, to access a special internal DR, as shown in Table 6-81.
Page 535 Reset Logic One of the major functions of the GLCP is to control the resetting of the AMD Geode LX processor. There are two methods to reset the processor: either by a hard reset using the input signal RESET#, or by a soft reset by writing to an internal MSR in the GLCP.
Page 536: Figure 6-56. Processor Clock Generation
6.13.4.3 GIO_PCI The GIO_PCI module drives the values of the system inter- face signals. Table 6-83 on page 537 shows the source of each output signal in each of the AMD Geode companion device modes. GeodeLink™ Control Processor CPU Core...
Page 537: Figure 6-57. Gio Interface Block Diagram
GL Clock Control PCI_RAW_CLK GLCP_SUSPA Figure 6-57. GIO Interface Block Diagram GIO Output GIO_SUSP GIO_SUSPA GIO_IRQ13 AMD Geode™ LX Processors Data Book GLIU Slave I/F IRQ13_GL LGCY_GL GIO_GLIU SMI_GL GIO_PCI Table 6-83. GIO_PCI Outputs Mode A SUSP# pin in serial mode...
Page 538: Table 6-84. Cis Signaling Protocol
Back to back serial packets can occur once the entire serial packet has completed. The AMD Geode LX processor decoded signals are guaran- teed to transition only after the entire completion of the packet, although they may transition during the transmis- sion of the packet.
Page 539: Geodelink™ Control Processor Register Descriptions
Acknowledge (GLCP_CLK4ACK) 4C000014h GLCP System Reset and PLL Control (GLCP_SYS_RSTPLL) AMD Geode™ LX Processors Data Book 33234H tables that include reset values and page references where the bit descriptions are provided. Note: The MSR address is derived from the perspective of the CPU Core.
Page 540 00000000_00000002h 00000000_000000xxh 00000000_000000Fh 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h AMD Geode™ LX Processors Data Book Reference Page 557 Page 559 Page 559 Page 560 Page 560 Page 561 Page 561 Page 562 Page 562 Page 563 Page 562...
Page 541 RSVD Reserved. Reads as 0. 23:8 DEV_ID Device ID. Identifies device (0024h). REV_ID Revision ID. Identifies device revision. See AMD Geode™ LX Processors Specification Update document for value. 6.14.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG) MSR Address 4C002001h Type Reset Value...
Page 542 SMI Debug Mask. If clear, enables debug logic to generate an ASMI. SMI_ERR_MASK SMI Error Mask. If clear, then any GLIU device error signal (including GLCP) causes an ASMI. GeodeLink™ Control Processor Register Descriptions GLD_MSR_SMI Register Map RSVD GLD_MSR_SMI Bit Descriptions RSVD AMD Geode™ LX Processors Data Book...
Page 543 ERR_SIZE ERR_TYPE 31:4 RSVD ERR_SYSPLL_MASK ERR_DOTPLL_MASK ERR_SIZE_MASK ERR_TYPE_MASK AMD Geode™ LX Processors Data Book GLD_MSR_ERROR Register Map RSVD RSVD GLD_MSR_ERROR Bit Descriptions Description Reserved. Error System PLL. System PLL lock signal was active when POR was inactive. Writing 1 clears error; 0 leaves unchanged.
Page 544 6.14.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG) MSR Address 4C002005h Type Reset Value 00000000_00000000h This register is reserved for internal use by AMD and should not be written to. GeodeLink™ Control Processor Register Descriptions GLD_MSR_PM Register Map RSVD RSVD GLD_MSR_PM Bit Descriptions...
Page 545 AES Core Functional Clock Off. When set, disables AES encryption/decryption clock. AESGLIU AES GLIU Clock Off. When set, disables AES GLIU interface clock. AESEE AES EEPROM Clock Off. When set, disables AES EEPROM clock. AMD Geode™ LX Processors Data Book GLCP_CLK_DIS_DELAY Register Map RSVD CLK_DELAY GLCP_PMCLKDISABLE Register Map RSVD...
Page 546 CPU to IPIPE Clock Off. When set, disable CPU clock to IPIPE block. FPUFAST FPU Fast Clock Off. When set, disables the fast FPU clock. FPUSLOW FPU Clock Off. When set, disables the slow CPU clock to FPU. GeodeLink™ Control Processor Register Descriptions AMD Geode™ LX Processors Data Book...
Page 547 Type Reset Value 00000000_00000001h This read only register is used to track various fab, process, and product family parameters. It is meant for AMD internal use only. Reads return reset value. 6.14.2.4 GLCP Global Power Management Controls (GLCP_GLB_PM) MSR Address...
Page 548 6.14.2.5 GLCP Debug Output from Chip (GLCP_DBGOUT) MSR Address 4C00000Ch Type Reset Value 00000000 00000000h This register is reserved for internal use by AMD and should not be written to. 6.14.2.6 GLCP Processor Status (GLCP_PROCSTAT) MSR Address 4C00000Dh Type Reset Value Bootstrap Dependant Note that the names of these bits have the read status data before the "_"...
Page 549 Buffer Control for RAS[1:0]#, CAS[1:0]#, CKE[1:0], CS[3:0]#, WE[1:0]# drive select. 1: Half power. 0: Quarter power. B_MA Buffer Control for MA[13:0] and BA[1:0]. 0: Half power. 1: Full power. AMD Geode™ LX Processors Data Book GLCP_DOWSER Register Map SW Defined SW Defined GLCP_DOWSER Bit Descriptions GLCP_DELAY_CONTROLS Bit Definition 33234H...
Page 550 DLL Override Setting or Read Strobe Delay Adjust. When DLL Override is 1 this is the DQS overide delay. When DLL Override is 0 this is the offset adjust value. GeodeLink™ Control Processor Register Descriptions AMD Geode™ LX Processors Data Book...
Page 551 DCGLIU_0 DC GLIU Clock 0 Off. When set, disables DC GLIU Clock 0 (DC). RSVD Reserved. Unused bit, reads what was written, value written has no effect. AMD Geode™ LX Processors Data Book GLCP_CLKOFF Register Map RSVD GLCP_CLKOFF Bit Descriptions...
Page 552 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 See "GLCP_CLKOFF Bit Descriptions" on page 551 for bit descriptions. GeodeLink™ Control Processor Register Descriptions GLCP_CLKACTIVE Register Map RSVD AMD Geode™ LX Processors Data Book...
Page 553 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 See "GLCP_CLKOFF Bit Descriptions" on page 551 for bit descriptions. AMD Geode™ LX Processors Data Book GLCP_CLKDISABLE Register Map...
Page 554 GLIULOCK (RO) Lock (Read Only). Lock signal from the system PLL. The worst-case lock time for a AMD Geode™ LX processor PLL is 100 µs. CORELOCK Lock (Read Only). Lock signal from the system PLL. The worst-case lock time for a (RO) AMD Geode LX processor PLL is 100 µs.
Page 555 Chip Reset. When written to a 1, the chip enters reset and does not come out until the HOLD_COUNT (bits [23:16]) is reached. This register and the JTAG logic are not reset by CHIP_RESET, but otherwise the entire chip is reset. (Default = 0) AMD Geode™ LX Processors Data Book 33234H...
Page 556: Table 6-87. Bootstrap Bit Settings And Reset State Of Glcp_Sys_Rstpll (Pw1 And Irq13 = 0)
Reset Value 00000396_00001800h 00000208_03001802h 0000028A_03001804h 0000028E_03001806h 0000038E_03001808h 00000292_0300180Ah 00000392_0300180Ch 00000492_0300180Eh 00000294_03001810h 00000394_03001812h 00000494_03001814h 00000296_03001816h 00000396_03001818h 00000496_0300181Ah 00000596_0300181Ch 00000398_0300181Eh 00000498_03001820h 00000598_03001822h 0000039A_03001824h 0000049A_03001826h 0000059A_03001828h 0000039C_0300182Ah 0000049C_0300182Ch 0000059C_0300182Eh 0000039E_03001830h 0000049E_03001832h 0000059E_030001834h 000002A2_03001836h 000004A0_03001838h 000005A0_0300183Ah 000004A2_0300003Ch 000005A2_0300183Eh AMD Geode™ LX Processors Data Book...
Page 557: Table 6-88. Bootstrap Bit Settings And Reset State Of Glcp_Sys_Rstpll (Pw1 And Irq13 Vary)
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SWFLAGS AMD Geode™ LX Processors Data Book CORE GLIU Speed...
Page 558 PLL settings and observe LOCK before releasing this reset. Unlike the SYS_RSTPLL register, this bit is not required to be set before the other bits in this register affect the PLL. GeodeLink™ Control Processor Register Descriptions GLCP_DOTPLL Bit Descriptions AMD Geode™ LX Processors Data Book...
Page 559 Description 63:8 RSVD Reserved. Reads as 0. Major Revision. Identifies major silicon revision. See AMD Geode™ LX Processors Specification Update document for value. Minor Revision. Identifies minor silicon revision. See AMD Geode™ LX Processors Specification Update document for value. AMD Geode™ LX Processors Data Book...
Page 560 SMI handling or any other preparations. P_LVL2_IN (MSR 4C00001Ch[12]) can abort the suspend operation. MSR reads to this register return 0, but perform no further action. GeodeLink™ Control Processor Register Descriptions GLCP_CNT Register Map RSVD RSVD GLCP_CNT Bit Descriptions CLK_VAL AMD Geode™ LX Processors Data Book...
Page 561 16 to get the number of PCI clock cycles per period, thus SCALE = 3 and CLK_VAL = 5 will have the processor active for 240 PCI clocks and suspended for 480 PCI clocks. AMD Geode™ LX Processors Data Book GLCP_TH_SD Register Map RSVD...
Page 562 The GLCP’s GLIU maintains MSRs that control the source and value of the companion device system outputs. It also con- trols the current companion device mode. Read data returns GLD_MSR_CAP data. GeodeLink™ Control Processor Register Descriptions GLCP_TH_OD Register Map RSVD GLCP_TH_OD Bit Descriptions OFF_DELAY AMD Geode™ LX Processors Data Book...
Page 563 111: -2.5%. Adjust for Green DAC. 000: 0%. 011: 7.5%. 100: -10%. 111: -2.5%. Adjust for Red DAC. 000: 0%. 011: 7.5%. 100: -10%. 111: -2.5%. AMD Geode™ LX Processors Data Book GLCP_DAC Register Map RSVD GLCP_DAC Bit Descriptions 33234H...
Page 564 Description 63:1 RSVD Reserved. MSR_INIT MSR_INIT. Value of INIT signal driven to CPU. GeodeLink™ Control Processor Register Descriptions MSR_A20M Register Map RSVD RSVD MSR_A20M Bit Descriptions MSR_INIT Register Map RSVD RSVD MSR_INIT Bit Descriptions AMD Geode™ LX Processors Data Book...
Page 565 Value of INTR signal from GLIU0, Port 2 (GLIU) GLIU0_INT1 Value of INTR signal from GLIU0, Port 1 (GLMC). GLIU0_INT0 Value of INTR signal from GLIU0, Port 0 (GLIU). AMD Geode™ LX Processors Data Book MSR_INTAX Register Map RSVD MSR_INTAX Bit Descriptions 33234H...
Page 566: Geodelink™ Pci Bridge
• Capable of handling out of bound transactions immedi- ately after reset GeodeLink™ Interface Unit 1 (GLIU1) Request Data Request GeodeLink™ Interface FIFOs/Synchronization Transaction Forwarding PCI Bus Interface Figure 6-58. GLPCI Block Diagram GeodeLink™ PCI Bridge PCI Bus AMD Geode™ LX Processors Data Book...
Page 567 Atomic External MSR Access The companion device implements a mailbox scheme simi- lar to the AMD Geode LX processor. To access internal model specific registers on the AMD Geode companion device’s GLIU it is necessary to perform multiple PCI con- figuration cycles.
Page 568: Figure 6-59. Atomic Msr Accesses Across The Pci Bus
GLIU-port2 -> PCI-device-25 GLIU-port3 -> PCI-device-30 GLIU1 GLIU-port4 -> PCI-device-1 GLPCI PCI-device = 1 PCI-device = 25 GLPCI GLIU0 GLIU1 Device-B 2.4.2.5.1.x GeodeLink™ PCI Bridge PCI-device = 30 GLPCI GLIU0 GLIU1 GLIU2 Device-C 2.4.3.2.7.3 AMD Geode™ LX Processors Data Book...
Page 569: Table 6-89. Format For Accessing The Internal Pci Configuration Registers
PCI 2.2 specification) is used. To access the internal PCI configuration registers of the AMD Geode LX processor, the Configuration Address reg- ister (CONFIG_ADDRESS) must be written as a DWORD using the format shown in Table 6-89. Any other size will be interpreted as an I/O write to Port 0CF8h.
Page 570: Figure 6-60. Simple Round-Robin
(see Figure 6-60). There are three external REQ#/GNT# pairs, numbered 0 through 2, and an internal REQ#/GNT# pair for the CPU. REQ2#/GNT2# is reserved for the AMD Geode companion device (i.e., southbridge). Each requestor can be configured to be preemptable/non- preemptable (Figure 6-61), given a repeat-count attribute and given a grant-hold timeout attribute.
Page 571 When a tar- get abort occurs, the PCI Bus Interface block must return the expected amount of data with sufficient error signals. AMD Geode™ LX Processors Data Book 33234H 6.15.6.3 In-Bound Write Exceptions...
Page 572: Geodelink™ Pci Bridge Register Descriptions
00000000_00000000h 00FF0000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h 00000000_00000000h AMD Geode™ LX Processors Data Book Reference Page 574 Page 574 Page 575 Page 576 Page 577 Page 577 Reference Page 578 Page 581 Page 584 Page 584...
Page 573 GLPCI Memory Region 5 Configuration (GLPCI_R5) 5000201Eh GLPCI External MSR Access Configuration (GLPCI EXT_MSR) 5000201Fh GLPCI Spare 50002020h GLPCI General Purpose I/O (GLPCI_GPIO) AMD Geode™ LX Processors Data Book 33234H Reset Value Reference 00000000_00000000h Page 593 00000000_00000000h Page 594 00000000_00000000h...
Page 574 RSVD Reserved. Reserved for future use. 23:8 DEV_ID Device ID. Identifies device (1054h). REV_ID Revision ID. Identifies device revision. See AMD Geode™ LX Processors Specification Update document for value. 6.16.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG) MSR Address 50002001h Type Reset Value...
Page 575 Target Abort Received Mask. Clear to allow TARE (bit 17) to generate an ASMI. MARM Master Abort Received Mask. Clear to allow MARE (bit 16) to generate an ASMI. AMD Geode™ LX Processors Data Book GLD_MSR_SMI Register Map RSVD RSVD...
Page 576 Target Abort Received Mask. Clear to allow TARE (bit 17) to assert ERR. MARM Master Abort Received Mask. Clear to allow MARE (bit 16) to assert ERR. GLD_MSR_ERROR Register Map RSVD GLD_MSR_ERROR Bit Descriptions GeodeLink™ PCI Bridge Register Descriptions RSVD AMD Geode™ LX Processors Data Book...
Page 577 6.16.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG) MSR Address 50002005h Type Reset Value 00000000_00000000h This register is for AMD use only and should not be written to. AMD Geode™ LX Processors Data Book GLD_MSR_PM Register Map RSVD RSVD GLD_MSR_PM Bit Descriptions 33234H...
Page 578 SBRTH Southbridge In-Bound Read Threshold. Controls the timing for prefetching read data for the AMD Geode™ companion device. If the number of prefetched 32-bit WORDs reaches this threshold, a subsequent GLIU request will be generated to fetch the next cache line of read data. The status of the companion device’s GNT# pin (GNT2#) is sam- pled to determine when the companion device is generating an in-bound request.
Page 579 Target Abort Received ASMI. Allow reception of a PCI bus target abort to be reported in the TARE bit (MSR 50002002h[17]). 0: Disable. 1: Enable. AMD Geode™ LX Processors Data Book 00: 32 PCI clock edges 10: 8 PCI clock edges 01: 16 PCI clock edges...
Page 580 101: 64 clock cycles 110: 128 clock cycles 111: 256 clock cycles 100: 64 PCI clock edges 101: 128 PCI clock edges 110: 256 PCI clock edges 111: No timeout PCI clock PCI clock cycles. For AMD Geode™ LX Processors Data Book...
Page 581 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD AMD Geode™ LX Processors Data Book GLPCI_ARB Register Map RSVD...
Page 582 This bit does not change the round robin arbitration cycle, it only overrides repeat-count and grant-hold for other requestors. GeodeLink™ PCI Bridge Register Descriptions GLPCI_ARB Bit Definitions AMD Geode™ LX Processors Data Book...
Page 583 Parking Policy. When cleared to 0, the arbiter always parks the PCI bus on the AMD Geode™ LX processor. When set to 1, the arbiter parks the PCI bus on the last granted bus master. If this bit is set, the clock for the PCI-fast clock domain should not be gated.
Page 584 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD GeodeLink™ PCI Bridge Register Descriptions GLPCI_PBUS Register Map RSVD GLPCI_PBUS Bit Descriptions GLPCI_REN Register Map Spare AMD Geode™ LX Processors Data Book...
Page 585 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 AMD Geode™ LX Processors Data Book GLPCI_REN Bit Descriptions...
Page 586: Table 6-93. Region Properties
D8 Properties. Region properties for D8000 through DBFFF. 47:40 D4 Properties. Region Properties for D4000 through D7FFF. GeodeLink™ PCI Bridge Register Descriptions GLPCI_A0 Bit Descriptions Table 6-93. Region Properties GLPCI_C0 Register Map GLPCI_C0 Bit Descriptions AMD Geode™ LX Processors Data Book...
Page 587 E4 Properties. Region Properties for E4000 through E3FFF. E0 Properties. Region properties for E0000 through E3FFF. Note 1. See Table 6-93 on page 586 for region properties bit decodes. AMD Geode™ LX Processors Data Book GLPCI_C0 Bit Descriptions (Continued) GLPCI_E0 Register Map...
Page 588 Cache Disable. When set to 1, accesses are marked as non-coherent. When cleared to 0 accesses are marked as coherent. GeodeLink™ PCI Bridge Register Descriptions GLPCI_R0 Register Map RSVD GLPCI_R0 Bit Descriptions RSVD RSVD AMD Geode™ LX Processors Data Book...
Page 589 Discard Data. When set to 1, write access are accepted and discarded. Read accesses are ignored (master abort). Cache Disable. When set to 1, accesses are marked as non-coherent. When cleared to 0, accesses are marked as coherent. AMD Geode™ LX Processors Data Book GLPCI_R1 Register Map RSVD GLPCI_R1 Bit Descriptions...
Page 590 Cache Disable. When set to 1, accesses are marked as non-coherent. When cleared to 0, accesses are marked as coherent. GeodeLink™ PCI Bridge Register Descriptions GLPCI_R2 Register Map RSVD GLPCI_R2 Bit Descriptions RSVD RSVD AMD Geode™ LX Processors Data Book...
Page 591 Discard Data. When set to 1, write access are accepted and discarded. Read accesses are ignored (master abort). Cache Disable. When set to 1, accesses are marked as non-coherent. When cleared to 0, accesses are marked as coherent. AMD Geode™ LX Processors Data Book GLPCI_R3 Register Map RSVD GLPCI_R3 Bit Descriptions...
Page 592 Cache Disable. When set to 1, accesses are marked as non-coherent. When cleared to 0, accesses are marked as coherent. GeodeLink™ PCI Bridge Register Descriptions GLPCI_R4 Register Map RSVD GLPCI_R4 Bit Descriptions RSVD RSVD AMD Geode™ LX Processors Data Book...
Page 593 Discard Data. When set to 1, write access are accepted and discarded. Read accesses are ignored (master abort). Cache Disable. When set to 1, accesses are marked as non-coherent. When cleared to 0, accesses are marked as coherent. AMD Geode™ LX Processors Data Book GLPCI_R5 Register Map RSVD GLPCI_R5 Bit Descriptions...
Page 594 Note: MSR accesses addressed to Port 0 are handled directly by the GLPCI module. GeodeLink™ PCI Bridge Register Descriptions GLPCI_EXT_MSR Register Map DEVICE-7 FUNC-6 DEVICE-6 DEVICE-3 FUNC-2 DEVICE-2 GLPCI_EXT_MSR Bit Descriptions FUNC-5 DEVICE-5 FUNC-1 DEVICE-1 AMD Geode™ LX Processors Data Book...
Page 595 PCI read may be placed onto the GLIU. When this bit is cleared the out-bound read data may be placed onto the GLIU after the in-bound write data has been placed onto the GLIU. AMD Geode™ LX Processors Data Book GLPCI Spare Spare...
Page 596 Input 1 (Read Only). Filtered input from REQ1# pin. IN0 (RO) Input 0 (Read Only). Filtered input from GNT1# pin. GLPCI_GPIO Register Map RSVD GLPCI_GPIO Register Bit Descriptions GeodeLink™ PCI Bridge Register Descriptions SAMPDIV RSVD AMD Geode™ LX Processors Data Book...
Page 597: 7.0Electrical Specifications
20-kΩ (±10%) pull-up resistor can be used if desired. Absolute Maximum Ratings Table 7-1 lists absolute maximum ratings for the AMD Geode LX processor. Stresses beyond the listed ratings may cause permanent damage to the device. Exposure to conditions...
Page 598: Operating Conditions
DDR2 (1.8V) LX 600@0.7W Note 1. The AMD Geode LX 900@1.5W processor operates at 600 MHz, the AMD Geode LX 800@0.9W processor oper- ates at 500 MHz, the AMD Geode LX 700@0.8W processor operates at 433 MHz and the AMD Geode LX 600@.07W processor operates at 366 MHz.
Page 599: Dc Current
ON state: Typical Average Typical Average (Typ Avg) indicates the average current used by the AMD Geode LX processor while in the ON state, with no active power management. This measure- ment is comprised of two components: WinBench Business Graphics Test and Active Idle power measure- ments.
Page 600: Figure 7-1. Vmemlx Power Split
MEMSLP - Unterminated MEMSLP Note 1. The AMD Geode LX 900@1.5W processor operates at 600 MHz. Model numbers reflect performance as described here: http://www.amd.com/connectivitysolutions/geodelxbenchmark. T = Terminated and U = Unterminated. Note 2. Calculations are based on a 32.5/67.5 split between V termination resistors.
Page 601: Table 7-4. Amd Geode Lx 800@0.9W Processor Dc Currents
MEMSLP - Unterminated MEMSLP Note 1. The AMD Geode LX 800@0.9W processor operates at 500 MHz. Model numbers reflect performance as described here: http://www.amd.com/connectivitysolutions/geodelxbenchmark. T = Terminated and U = Unterminated. Note 2. Calculations are based on a 32.5/67.5 split between V termination resistors.
Page 602: Table 7-5. Amd Geode Lx 700@0.8W Processor Dc Currents
MEMSLP - Unterminated MEMSLP Note 1. The AMD Geode LX 700@0.8W processor operates at 433 MHz. Model numbers reflect performance as described here: http://www.amd.com/connectivitysolutions/geodelxbenchmark. T = Terminated and U = Unterminated. Note 2. Calculations are based on a 32.5/67.5 split between V termination resistors.
Page 603: Table 7-6. Amd Geode Lx 600@0.7W Processor Dc Currents
MEMSLP - Unterminated MEMSLP Note 1. The AMD Geode LX 600@0.7W processor operates at 366 MHz. Model numbers reflect performance as described here: http://www.amd.com/connectivitysolutions/geodelxbenchmark. T = Terminated and U = Unterminated. Note 2. Calculations are based on a 32.5/67.5 split between V termination resistors.
Page 604: Dc Characteristics
All DC parameters and current measurements in this section were measured under the operating conditions listed in Table 7-2 "Operating Conditions", unless otherwise noted. The signals associated with the seven signal buffer types on the AMD Geode LX processor, are shown Table 3-5 "Ball Assignments - Sorted by Ball Number" on page 26. Symbol...
Page 605 DDRCLK Output High Current, Note 1 24/Q3 24/Q5 24/Q7 DDR (BA[1:0], MA[13:0]) DDR (DQ[63:0], CKE[1:0], CS[3:0]#, RAS[1:0]#, CAS[1:0]#, WE[1:0]#, DQS[7:0], DQM[7:0], TLA[1:0] DDRCLK AMD Geode™ LX Processors Data Book Units -3.0 µA -3.0 µA -3.0 µA -3.0 µA -3.0 µA -3.0...
Page 606 24.0 24.0 16.0 15.2 10.0 15.0 is not used to drive high, I AMD Geode™ LX Processors Data Book Electrical Specifications Comments (Max) min = 11 mA with half- drive set for pad min = 8 mA with quarter- drive set for pad...
Page 607: Ac Characteristics
B = Minimum Output or Float Delay Specification C = Minimum Input Setup Specification D = Minimum Input Hold Specification Figure 7-2. Drive Level and Measurement Points for Switching Characteristics AMD Geode™ LX Processors Data Book MVREF: DDR:1.25V C to 85 50 Ω...
Page 608: Figure 7-3. Drive Level And Measurement Points For Switching Characteristics
VAL1,2 VAL1,2 Valid Output SU1,2 Valid Input Electrical Specifications Unit Comments 66 MHz 40% t 40% t Note 1 Note 1 Note 2 For PLL lock . Otherwise, V CORE CORE H1,2 AMD Geode™ LX Processors Data Book can be...
Page 609: Figure 7-4. Power Up Sequencing
Note 2. Output delay includes tristate-to-valid transitions and valid-to-tristate timing. SYSREF VAL1,2 Valid Output Outputs Inputs Figure 7-5. Drive Level and Measurement Points for Switching Characteristics AMD Geode™ LX Processors Data Book MVON RSTX Figure 7-4. Power Up Sequencing Table 7-9. PCI Interface Signals VAL1,2 Valid Output...
Page 610: Figure 7-6. Drive Level And Measurement Points For Switching Characteristics
Inputs Figure 7-6. Drive Level and Measurement Points for Switching Characteristics Table 7-10. VIP Interface Signals 12.5 VAL1,2 Valid Output SU1,2 Valid Input Electrical Specifications Unit Comments 80 MHz 45% t 45% t H1,2 AMD Geode™ LX Processors Data Book...
Page 611: Figure 7-7. Drive Level And Measurement Points For Switching Characteristics
HSYNC trigger. DOTCLK VAL1,2,3 Valid Output Outputs Figure 7-7. Drive Level and Measurement Points for Switching Characteristics AMD Geode™ LX Processors Data Book Table 7-11. Flat Panel Interface Signals VAL1,2,3 Valid Output 33234H Unit...
Page 612: Table 7-12. Crt Interface Signals
Electrical Specifications Unit Comments 350 MHz 45% t 45% t Note 1 Between any two signals Note 2 Units Comments Ω One each signal. One each signal. Ω This resistor should have a 1% tolerance. AMD Geode™ LX Processors Data Book...
Page 613: Table 7-14. Crt Display Analog (Dac) Characteristics
Note 2. Full-scale transition time is measured from 50% of full-scale transition until output remaining within 1LSB of target. Note 3. Timing measurements are made with a 75 Ω doubly-terminated load, with VEXT Note 4. 10% to 90% of full-scale transition. AMD Geode™ LX Processors Data Book Units 1.25 18.67...
Page 614: Table 7-15. Memory (Ddr) Interface Signals
0.75*t 0.75*t -0.4 -0.25*t +0.5 0.25*t +0.5 0.25*t 0.25*t -0.4 +0.4 VAL2 AMD Geode™ LX Processors Data Book Electrical Specifications Unit Comments Note 2 48% t 48% t Guaranteed by design Note 2, Note 3 Same as t Note 4...
Page 615: Figure 7-8. Ddr Write Timing Measurement Points
Electrical Specifications SDCLK0P SDCLK[5:1]P SDCLK[5:0]N DQS Outputs Valid Output Non-DQ Outputs DQ Outputs Figure 7-8. DDR Write Timing Measurement Points AMD Geode™ LX Processors Data Book DEL1 SKEW1 DEL2 VAL2 VAL2 Valid Output VAL1 VAL1 33234H SKEW1...
Page 616: Figure 7-9. Ddr Read Timing Measurement Points
33234H SDCLK0 DQSCK DQS ‘Late’ Input DQSCK DQS ‘Early’ Input DQS[n] Input SKEW2 other DQS Input DQ Inputs associated with DQS[n] Figure 7-9. DDR Read Timing Measurement Points SKEW2 DQSQh DQSQs Electrical Specifications AMD Geode™ LX Processors Data Book...
Page 617: Table 7-16. Jtag Interface Signals
All chip I/O Output Valid Delay time from TCLK falling edge - boundary scan test Note 1. TCLK limited during functional mode to 100 MHz or 1/4 of the memory data frequency. AMD Geode™ LX Processors Data Book Table 7-16. JTAG Interface Signals GLBus 33234H...
Page 618 33234H Electrical Specifications AMD Geode™ LX Processors Data Book...
Page 619: 8.0Instruction Set
• Processor Core Instruction Set - listed in Section 8.3 on page 633. • MMX™, FPU, and AMD 3DNow!™ Instruction Sets (including extensions) - listed in Section 8.4 on page 658. In the above listed sections are tables that provide information on the instruction encoding, and the instruction clock counts for each instruction.
Page 620: Table 8-2. Instruction Fields
Make operand size attribute the inverse of the default. Make address size attribute the inverse of the default. Assert LOCK# internal hardware signal. Repeat the following string instruction. Repeat the following string instruction. Instruction Set AMD Geode™ LX Processors Data Book...
Page 621: Table 8-4. W Field Encoding
8 bits wide and is sign-extended to match the operand size of the opcode. See Table 8-6. s Field 8-Bit Operand Size 0 (or not present) AMD Geode™ LX Processors Data Book Table 8-4. w Field Encoding Operand Size 16-Bit Data Operations...
Page 622: Table 8-7. Eee Field Encoding
DS:[EAX] DS:[ECX] DS:[EDX] DS:[EBX] s-i-b is present (See Table 8-15 on page 626) DS:[d32] DS:[ESI] DS:[EDI] Instruction Set Base Register 32-Bit Address Mode with mod r/m Byte and No s-i-b Byte Present (Note 1) AMD Geode™ LX Processors Data Book...
Page 623: Table 8-9. General Registers Selected By Mod R/M Fields And W Field
8-bit displacement, d16 refers to 16-bit displacement, and d32 refers to a 32-bit displacement. Table 8-9. General Registers Selected by mod r/m Fields and w Field AMD Geode™ LX Processors Data Book 32-Bit Address Mode with mod r/m Byte and...
Page 624: Table 8-10. Reg Field
Field Table 8-10. reg Field 16-Bit Operation w = 1 Table 8-11. sreg2 Field Encoding Segment Register Selected Segment Register Selected Undefined Undefined Instruction Set 32-Bit Operation w = 0 w = 1 AMD Geode™ LX Processors Data Book...
Page 625: Table 8-13. Ss Field Encoding
The index field (Table 8-14) specifies the index register used by the offset mechanism for offset address calculation. When no index register is used (index field = 100), the ss value must be 00 or the effective address is undefined. Index Field AMD Geode™ LX Processors Data Book Table 8-13. ss Field Encoding Scale Factor Table 8-14.
Page 626: Table 8-15. Mod Base Field Encoding
DS:[EAX+(scaled index)+d8] DS:[ECX+(scaled index)+d8] DS:[EDX+(scaled index)+d8] DS:[EBX+(scaled index)+d8] SS:[ESP+(scaled index)+d8] SS:[EBP+(scaled index)+d8] DS:[ESI+(scaled index)+d8] DS:[EDI+(scaled index)+d8] DS:[EAX+(scaled index)+d32] DS:[ECX+(scaled index)+d32] DS:[EDX+(scaled index)+d32] DS:[EBX+(scaled index)+d32] SS:[ESP+(scaled index)+d32] SS:[EBP+(scaled index)+d32] DS:[ESI+(scaled index)+d32] DS:[EDI+(scaled index)+d32] Instruction Set AMD Geode™ LX Processors Data Book...
Page 627: Cpuid Instruction Set
Table 8-17. CPUID Instruction with EAX = 00000001h Returned Register Contents Description 000005Axh Type/Family/Model/Step 00000400h Reserved 00000000h Reserved 0088A93Dh Standard Feature Flags AMD Geode™ LX Processors Data Book Description Maximum Standard Level Vendor ID String 1 Vendor ID String 2 Vendor ID String 3 33234H Comment Comment...
Page 628: Table 8-18. Cpuid Instruction Codes With Eax = 00000000
EDX[2] DE. Debugging Extension Instruction Set Comment May change with CPU revision Not supported Not supported Not supported Not supported Not supported Not supported Not supported Not supported Not supported Not supported Not supported AMD Geode™ LX Processors Data Book...
Page 629: Table 8-19. Cpuid Instruction With Eax = 80000000H
Contents Description 000005Axh Type/Family/Model/Step 00000000h Reserved 00000000h Reserved C0C0A13Dh Feature Flags AMD Geode™ LX Processors Data Book Description Maximum Extended CPUID Level Vendor ID String 1 Vendor ID String 2 Vendor ID String 3 33234H Comment Not supported Comment Comment...
Page 630: Table 8-21. Cpuid Instruction Codes With Eax = 80000001H
Instruction Set Comment May change with CPU revision Not supported Not supported Not supported Not supported Not supported Not supported Not supported Not supported Not supported Not supported Not supported Not supported Not supported AMD Geode™ LX Processors Data Book...
Page 631: Table 8-22. Cpuid Instruction With Eax = 80000002H, 80000003H, Or 80000004H
{b ro} EAX = 80000004h 4D412079h {MA y} 43502044h {CP D} 00000053h 00000000h AMD Geode™ LX Processors Data Book Description Comment CPU Marketing Name 1a CPU Marketing Name 1b CPU Marketing Name 2a CPU Marketing Name 2b CPU Marketing Name 3a...
Page 632: Table 8-23. Cpuid Instruction With Eax = 80000005H
Decodes to eight fully associative code TLB and eight fully associative data TLB entries. Indicates 16 KB four-way associative with 32-byte lines for data cache. These encodings follow the AMD report- ing method. Indicates 16 KB four-way associative with 32-byte lines for code cache.
Page 633: Processor Core Instruction Set
Instruction Set Processor Core Instruction Set The instruction set for the AMD Geode LX processor core is summarized in Table 8-26. The table uses several symbols and abbreviations that are described next and listed in Table 8-25. 8.3.1 Opcodes Opcodes are given as hex values except when they appear within brackets as binary values.
Page 634: Table 8-26. Processor Core Instruction Set
Notes Flags O D I T S Z A P C Real Prot’d F F F F F F F F F Mode Mode - u u x u u x b, e g,h,j,k, AMD Geode™ LX Processors Data Book...
Page 635 CMOVNO Move if No Overflow Register, Register/Memory CMOVP/CMOVPE Move if Parity/Parity Even Register, Register/Memory CMOVNP/CMOVPO Move if Not Parity/Parity Odd Register, Register/Memory CMOVS Move if Sign Register, Register/Memory AMD Geode™ LX Processors Data Book Clock Count (Reg/Cache Hit) Real Prot’d Opcode Mode Mode...
Page 636 T S Z A P C Real Prot’d F F F F F F F F F Mode Mode u u - 0 0 0 0 0 0 0 0 0 s, u s, u u u - AMD Geode™ LX Processors Data Book...
Page 637 8-bit Displacement Full Displacement Register/Memory Indirect Within Segment Direct Intersegment Indirect Intersegment JNB/JAE/JNC Jump on Not Below/Above or Equal/Not Carry 8-bit Displacement Full Displacement AMD Geode™ LX Processors Data Book Clock Count (Reg/Cache Hit) Real Prot’d Opcode Mode Mode F [011w] [mod 101 r/m]...
Page 638 E2 + Instruction Set Notes Flags O D I T S Z A P C Real Prot’d F F F F F F F F F Mode Mode g,h,j,p h,i,j h,i,j h,i,j h,i,j g,h,j,l AMD Geode™ LX Processors Data Book...
Page 639 NOT Boolean Complement OIO Official Invalid Opcode OR Boolean OR Register to Register Register to Memory Memory to Register Immediate to Register/Memory Immediate to Accumulator AMD Geode™ LX Processors Data Book Clock Count (Reg/Cache Hit) Real Prot’d Opcode Mode Mode...
Page 640 0F 32 0F 31 Instruction Set Notes Flags O D I T S Z A P C Real Prot’d F F F F F F F F F Mode Mode h,i,j s, u s, u AMD Geode™ LX Processors Data Book...
Page 641 Register/Memory by Immediate RSDC Restore Segment Register and Descriptor RSLDT Restore LDTR and Descriptor RSTS Restore TSR and Descriptor RSM Resume from SMM Mode SAHF Store AH in FLAGS AMD Geode™ LX Processors Data Book Clock Count (Reg/Cache Hit) Real Prot’d Opcode...
Page 642 0F 9A [mod 000 r/m] 0F 98 [mod 000 r/m] Instruction Set Notes Flags O D I T S Z A P C Real Prot’d F F F F F F F F F Mode Mode AMD Geode™ LX Processors Data Book...
Page 643 Immediate Data and Accumulator VERR Verify Read Access To Register/Memory VERW Verify Write Access To Register/Memory WAIT Wait Until FPU Not Busy WBINVD Writeback and Invalidate Cache AMD Geode™ LX Processors Data Book Clock Count (Reg/Cache Hit) Real Prot’d Opcode Mode...
Page 644 The instructions, RDTSC, RDPMC, and RDMSR all have the effect of serializing with pending memory requests. For example, a RDTSC will not complete until any pending line fills or prefetches have completed. This is an artifact of the AMD Geode CPU and GeodeLink architecture since out-of-order read responses are not supported.
Page 645 The destination of a JMP, CALL, INT, RET, or IRET must be in the defined limit of a code segment or an exception 13 fault occurs. Issue s applies to AMD-specific SMM and DMM instructions: An invalid opcode exception 6 occurs unless the current privilege level is zero (most privileged) and either the instruc- tion is enabled in SMM_CTL, the instruction is enabled in DMM_CTL, the processor is in system management mode, or the processor is in debug management mode.
Page 646 CS.LIMIT <= DMM_LIMIT | 32’hfff; CS.G <= 1’b1; EFLAGS <= 32’h00000002; DMM <= 1; Jump to CS at offset of 0; Clocks Description 50-52 Enter DMM and call the DMI handler AMD Geode™ LX Processors Data Book Instruction Set...
Page 647 The EFlags are pushed to the stack, and may then be modified before the debug exception handler is called. The EFlags may be restored by the debug exception handler’s IRET. Notes Debuggers should not insert ICEBP instruction immediately after an instruction that alters the stack segment (MOV_SS). AMD Geode™ LX Processors Data Book XDR6 XDR7 E W A...
Page 648 If the current privilege level is not 0. Notes These are not the Intel or AMD Geode LX processor test registers. Writing to a test register has no side effects. Reading from a test register has no side effects. The reg field within the ModR/M byte specifies which of the test registers is involved. Reg values of 0, 1, 2, 3, 4, 5, 6, 7 specify TR0, TR1, TR2, TR3, TR4, TR5, TR6, and TR7 respectively.
Page 649 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 SS FLAGS 0 Av CS FLAGS 0 Av Flags Affected All bits of the EFlags register is restored from the DMM header. AMD Geode™ LX Processors Data Book Clocks Description Return from DMI XDR6 XDR7 E W A...
Page 650 External interrupts, single-step traps, and debug exceptions are not taken between a RSDC CS instruction and the RSLDT instruction (Section 8.3.4.6 on page 651). Clocks Description Restore descriptor from memory SELECTOR[15:3] LIMIT[19:16] Instruction Set E W A BASE[23:16] LIMIT[15:0] AMD Geode™ LX Processors Data Book...
Page 651 The reg field within the mod r/m byte must be zero for the RSLDT instruction to be recognized. The RSLDT instruction does not check its memory operand for validity. Care should be taken to always load valid data into the LDT. AMD Geode™ LX Processors Data Book Clocks Description...
Page 652 DMM. Clocks Description Return from SMI EFlags CURRENT_IP NEXT_IP Code Segment Selector 1 Cf R CS_BASE CS_LIMIT[19:0] E W A I/O SIZE I/O_DATA SMM_CTL Instruction Set INDEX SMM Flags I/O ADDRESS[15:0] AMD Geode™ LX Processors Data Book...
Page 653 AL <= {8{CF}}; Description IF the EFlags CF is set, then the SETALC instruction sets AL to FFh. Otherwise, SETALC sets AL to FFh. Flags Affected None. AMD Geode™ LX Processors Data Book Clocks Description Restore TS from memory SELECTOR[15:3]...
Page 654 CS.LIMIT <= SMM_LIMIT | 32’hfff; CS.G <= 1’b1; EFLAGS <= 32’h00000002; SMM_CTL <= {SMM_CTL[31:3],1’b0, SMM_CTL[1], 1’b0}; SMM <= 1; Jump to CS at offset of 0; Clocks Description Enter SMM and call the SMI handler AMD Geode™ LX Processors Data Book Instruction Set...
Page 655 CURRENT_IP field of the SMM header will point to the SMINT instruction. The NEXT_IP field of the SMM header will point to the instruction following the SMINT instruction. The S bit of the SMM header will be set. AMD Geode™ LX Processors Data Book EFlags...
Page 656 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 BASE[31:24] BASE[15:0] Flags Affected None. Clocks Description Restore descriptor from memory SELECTOR[15:3] LIMIT[19:16] Clocks Description Save LDT to memory SELECTOR[15:3] LIMIT[19:16] Instruction Set E W A BASE[23:16] LIMIT[15:0] E W A BASE[23:16] LIMIT[15:0] AMD Geode™ LX Processors Data Book...
Page 657 If current privilege level is not 0, or the SMM_INST_EN = 0 and if the processor is not in SMM and if the processor is not in DMM. Notes The reg field within the mod r/m byte must be zero for the SVTS instruction to be recognized. AMD Geode™ LX Processors Data Book Clocks Description Save TS to memory...
Page 658: Mmx™, Fpu, And Amd 3Dnow!™ Technology Instructions Sets
The MMX instruction set (including extensions) is summarized in Table 8-28. The FPU instruction set is summarized in Table 8-29. The AMD 3DNow! instruction set (including extensions) is summarized in Table 8-30. The abbreviations used in the instruction sets are listed in Table 8-27.
Page 659 Instruction Set Table 8-27. MMX™, FPU, and AMD 3DNow!™ Instruction Set Table Legend Abbreviation Description windex 1 (imm8) The range given by [index1 (imm8) + 15: index1 (imm8)]. windex 2 (imm8) The range given by [index2 (imm8) + 15: index2 (imm8)].
Page 660: Table 8-28. Mmx™ Instruction Set
[sign word]) MMX reg 1 [byte] <--- sat --- (MMX reg 1 [byte] + MMX reg 2 [byte]) MMX reg [byte] <--- sat --- (memory [byte] + MMX reg [byte]) Instruction Set Clock Ct Notes AMD Geode™ LX Processors Data Book...
Page 661 MMX Register 2 to MMX Register 1 0F64 [11 mm1 mm2] Memory with MMX Register 0F64 [mod mm r/m] AMD Geode™ LX Processors Data Book Opcode Operation MMX reg 1 [word] <--- sat --- (MMX reg 1 [word] + MMX reg 2 [word]) MMX reg [word] <--- sat --- (memory [word] + MMX reg [word])
Page 662 MMX reg [byte] <--- MMX reg [byte] --- if (MMX reg [byte] Memory64 [byte]) MMX reg [byte] <--- Memory64 [byte] --- if (MMX reg [byte] > Memory64 [byte]) Instruction Set Clock Ct Notes > Memory64 [sign > AMD Geode™ LX Processors Data Book...
Page 663 MMX Register1 with MMX Register2 0FF6 [11 mm1 mm2] MMX Register with Memory64 0FF6 [mod mm r/m] AMD Geode™ LX Processors Data Book Opcode Operation MMX reg 1 [word] <--- MMX reg 1 [word] --- if (MMX reg 1 <...
Page 664 MMX reg [word] <--- MMX reg [word] shift right by memory [word], shifting in zeroes MMX reg [word] <--- MMX reg [word] shift right by imm [word], shifting in zeroes Instruction Set Clock Ct Notes AMD Geode™ LX Processors Data Book...
Page 665 MMX Register 2 to MMX Register 1 0F61 [11 mm1 mm2] Memory to MMX Register 0F61 [11 mm reg] AMD Geode™ LX Processors Data Book Opcode Operation MMX reg 1 [byte] <--- MMX reg 1 [byte] - MMX reg 2 [byte] MMX reg [byte] <--- MMX reg [byte] - memory [byte]...
Page 666 MMX reg 1 [qword] --- MMX reg 1 [qword], <--- logic exclusive OR MMX reg 2 [qword] MMX reg [qword] --- memory64 [qword], <--- logic exclusive OR MMX reg [qword] Instruction Set Clock Ct Notes AMD Geode™ LX Processors Data Book...
Page 667: Table 8-29. Fpu Instruction Set
FICOM Floating Point Integer Compare 32-bit integer 16-bit integer FICOMP Floating Point Integer Compare, Pop 32-bit integer 16-bit integer FCOS Function Evaluation: Cos(x) AMD Geode™ LX Processors Data Book Table 8-29. FPU Instruction Set Opcode Operation D9 F0 TOS <--- 2 D9 E1 TOS <--- | TOS |...
Page 668 M.WI D9 D0 No Operation Instruction Set Clock Ct Single/Dbl (or extended) Notes 12/47 12/47 12/47 12/47 12/47 12/47 12/47 12/47 12/47 12/47 13/48 13/48 13/48 13/48 1/10 1/10 1/10 1/10 1/10 2/11 2/11 AMD Geode™ LX Processors Data Book...
Page 669 FSUBR Floating Point Subtract Reverse Top of Stack 80-bit Register 64-bit Real 32-bit Real FSUBRP Floating Point Subtract Reverse, Pop AMD Geode™ LX Processors Data Book Opcode Operation D9 F3 ST(1) <--- ATAN[ST(1) / TOS]; then pop TOS D9 F8 TOS <--- Rem[TOS / ST(1)]...
Page 670 These instructions are executed in a separate unit and execute in parallel with other multicycle instructions. The AMD Geode LX processor performs PFRCP and PFRSQRT to 24-bit accuracy in one cycle, so these instructions are unnecessary. They are treated as a move.
Page 671: Table 8-30. Amd 3Dnow!™ Technology Instruction Set
Instruction Set Table 8-30. AMD 3DNow!™ Technology Instruction Set AMD 3DNow!™ Instructions FEMMS Faster Exit of the MMX or 0F0E 3DNow! State PAVGUSB Average of Unsigned Packed 8-Bit Values MMX Register 1 with MMX Register2 0F0F [11 mm1 mm2] BF...
Page 672 33234H Table 8-30. AMD 3DNow!™ Technology Instruction Set (Continued) AMD 3DNow!™ Instructions PFMAX Packed Floating-Point MAXimum MMX Register1 with MMX Register2 0F0F [11 mm1 mm2] A4 MMX Register with Memory64 0F0F [mod mm r/m] PFMIN Packed Floating - Point MINimum...
Page 673 These instructions must wait for the FPU pipeline to flush. Cycle count depends on what instructions are in the pipe- line. The AMD Geode LX processor performs PFRCP and PFRSQRT to 24-bit accuracy in one cycle, so these instructions are unnecessary. They are treated as a move.
Page 674 Page fault. Unaligned access. Illegal opcode. Notes This instruction is enabled by the INV_3DNOW_ENABLE bit (bit 1) of the ID_CONFIG MSR (MSR 00001250h). Clocks Description Approximate reciprocal Clocks Description Approximate reciprocal square root AMD Geode™ LX Processors Data Book Instruction Set...
Page 675: 9.0Package Specifications
Package Specifications 33234H 9.0Package Specifications Physical Dimensions The figures in this section provide the mechanical package outline for the BGU481 (481-terminal Ball Grid Array Cavity Up) Figure 9-1. BGU481 Top/Side View/Dimensions AMD Geode™ LX Processors Data Book...
Page 676: Figure 9-2. Bgu481 Bottom View/Dimensions
33234H Package Specifications Figure 9-2. BGU481 Bottom View/Dimensions AMD Geode™ LX Processors Data Book...
Page 677: Appendix Asupport Documentation
Order Information Ordering information for the AMD Geode™ LX processors is contained in this section. The ordering part number (OPN) is formed by a combination of elements. An example of the OPN is shown in Figure A-1. Valid OPN combinations are pro- vided in Table A-1 on page 678.
Page 678: Table A-1. Valid Opn Combinations
MTDP Indicator θ Note: JC = 3.7° C/W Consult your local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations possibly not listed. Table A-1. Valid OPN Combinations Package Operating System Bus...
Page 679: Data Book Revision History
Appendix A: Data Book Revision History Data Book Revision History This document is a report of the revision/creation process of the data book for the AMD Geode™ LX processors. Any revi- sion (i.e., additions, deletions, parameter corrections, etc.) are recorded in the table(s) below.
Page 680 One AMD Place • P.O. Box 3453 • Sunnyvale, CA 94088-3453 USA • Tel: 408-749-4000 or 800-538-8450 • TWX: 910-339-9280 • TELEX: 34-6306...

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AMD Geode LX 600@0.7W Data Book

List of Figures

List of Tables

1 0Overview

2 0Architecture Overview

3 0Signal Definitions

4 0Geodelink™ Interface Unit

5 0CPU Core

6 0Integrated Functions

7 0Electrical Specifications

8 0Instruction Set

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