AMD Geode LX 600@0.7W Data Book page 501

Video Input Port Register Descriptions
6.10.2.16 VIP Task B Video Odd Base/Horizontal Start (VIP_TASK_B_VID_ODD_BASE_HORIZ_START)
VIP Memory Offset 3Ch
Type R/W
Reset Value 00000000h
VIP_TASK_B_VID_ODD_BASE_HORIZ_START Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
VIP_TASK_B_VID_ODD_BASE_HORIZ_START Bit Descriptions
Bit Name
31:0 TASK_B_VID_
ODD_BASE
11:0 HORIZ_START
6.10.2.17 VIP Task B VBI Even Base/VBI End (VIP_TASK_B_VBI_EVEN_BASE_VBI_END)
VIP Memory Offset 40h
Type R/W
Reset Value 00000000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
VIP_TASK_B_VBI_EVEN_BASE_VBI_END Bit Descriptions
Bit Name
31:0 TASK_B_VBI_
DATA_EVEN_
BASE_VBI_
END
AMD Geode™ LX Processors Data Book
TASK_B_VID_ODD_BASE_HORIZ_START (601 type modes)
Description
Task B Video Odd Base Address. This register specifies the base address in graphics
memory where odd video field data is stored. Changes to this register take effect at the
beginning of the next field. This value must be 32-byte aligned. (Bits[4:0] are required to
be 00000.)
Note: This register is double buffered. When a new value is written to this register, the
new value is placed in a special pending register, and the "Base Register Not
Updated" bit (VIP Memory Offset 08h[16]) is set to 1. The Video Data Odd Base
Address register is not updated at this point. When the first data of the next field
is captured, the pending values of all base registers are written to the appropriate
base registers, and the Base Register Not Updated bit is cleared.
Horizontal Start. This register is redefined in BT.601 mode. In BT.601 type input modes
timing is derived from the external HSYNC and VSYNC inputs. This value specifies
where video data starts for the line. See Figure 6-47 "BT.601 Mode Horizontal Timing" on
page 472 for programing information.
VIP_TASK_B_VBI_EVEN_BASE_VBI_END Register Map
TASK_B_VBI_DATA_EVEN_BASE_VBI_END (for 601 type modes)
Description
Task B VBI Even Base Address. This register specifies the base address in graphics
memory where VBI data for even fields is stored. Changes to this register take effect at
the beginning of the next field. This value must be 32-byte aligned. (Bits [4:0] are
required to be 00000.)
Note: This register is double buffered. When a new value is written to this register, the
new value is placed in a special pending register, and the Base Register Not
Updated bit (VIP Memory Offset 08h[16]) is set to 1. The VBI Odd Base Address
register is not updated at this point. When the first data of the next field is cap-
tured, the pending values of all base registers are written to the appropriate base
registers, and the VBI Base Register Not Updated bit is cleared.
33234H
9 8 7 6 5 4 3 2
9 8 7 6 5 4 3 2
1 0
1 0
501