Geodelink™ Memory Controller Register Descriptions; Table 6-5. Standard Geodelink™ Device Msrs Summary; Table 6-6. Glmc Specific Msr Summary - AMD Geode LX 600@0.7W Data Book

GeodeLink™ Memory Controller Register Descriptions
6.2 GeodeLink™ Memory Controller Register Descriptions
All GLMC registers are Model Specific Registers (MSRs)
and are accessed via the RDMSR and WRMSR instruc-
tions.
The registers associated with the GLMC are the Standard
GeodeLink Device (GLD) MSRs and GLMC Specific
MSRs. Table 6-5 and Table 6-6 are register summary
MSR
Address Type
20002000h RO
20002001h ---
20002002h R/W
20002003h R/W
20002004h R/W
20002005h R/W
MSR
Address Type
20000010h RO
20000011h RO
20000012h RO
20000013h RO
20000014h RO
20000015h RO
20000016h RO
20000017 RO
20000018h R/W
20000019h R/W
2000001Ah R/W
2000001Bh RO
2000001Ch R/W
2000001Dh R/W
2000001Eh RO
AMD Geode™ LX Processors Data Book
Table 6-5. Standard GeodeLink™ Device MSRs Summary
Register Name
GLD Capabilities MSR (GLD_MSR_CAP)
GLD Master Configuration MSR
(GLD_MSR_CONFIG) - Not Used
GLD SMI MSR (GLD_MSR_SMI)
GLD Error MSR (GLD_MSR_ERROR)
GLD Power Management (GLD_MSR_PM)
GLD Diagnostic (GLD_MSR_DIAG)

Table 6-6. GLMC Specific MSR Summary

Register Name
Row Addresses Bank0 DIMM0, Bank1 DIMM0
(MC_CF_BANK01)
Row Addresses Bank2 DIMM0, Bank3 DIMM0
(MC_CF_BANK23)
Row Addresses Bank4 DIMM0, Bank5 DIMM0
(MC_CF_BANK45)
Row Addresses Bank6 DIMM0, Bank7 DIMM0
(MC_CF_BANK67)
Row Addresses Bank0 DIMM1, Bank1 DIMM0
(MC_CF_BANK89)
Row Addresses Bank2 DIMM1, Bank3 DIMM1
(MC_CF_BANKAB)
Row Addresses Bank4 DIMM1, Bank5 DIMM1
(MC_CF_BANKCD)
Row Addresses Bank6 DIMM1, Bank7 DIMM1
(MC_CF_BANKEF)
Refresh and SDRAM Program
(MC_CF07_DATA)
Timing and Mode Program (MC_CF8F_DATA)
Feature Enables (MC_CF1017_DATA)
Performance Counters (MC_CFPERF_CNT1)
Counter and CAS Control (MC_PERCNT2)
Clocking and Debug (MC_CFCLK_DBUG)
Page Open Status (MC_CFPG_OPEN)
tables that include reset values and page references where
the bit descriptions are provided.
Note: MSR addresses are documented using the CPU
Core as the source. Refer to Section 4.1 "MSR
Set" on page 45 for further details.
Reset Value
00000000_000204xxh
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
Reset Value
xxxxxxxx_xxxxxxxxh
xxxxxxxx_xxxxxxxxh
xxxxxxxx_xxxxxxxxh
xxxxxxxx_xxxxxxxxh
xxxxxxxx_xxxxxxxxh
xxxxxxxx_xxxxxxxxh
xxxxxxxx_xxxxxxxxh
xxxxxxxx_xxxxxxxxh
10071007_00000040h
18000008_287337A3h
00000000_11080001h
00000000_00000000h
00000000_00FF00FFh
00000000_00001300h
00000000_0000FFFFh
33234H
Reference
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