5.0Cpu Core; Core Processor Initialization; Table 5-1. Initialized Core Register Controls - AMD Geode LX 600@0.7W Data Book

CPU Core
This section describes the internal operations of the
AMD Geode™ LX processor's CPU Core from a program-
mer's point of view. It includes a description of the tradi-
tional "core" processing and FPU operations. The
integrated function registers are described in the next
chapter.
The primary register sets within the processor core include:
• Application Register Set
• System Register Set
5.1

Core Processor Initialization

The CPU Core is initialized when the RESET# (Reset) sig-
nal is asserted. The CPU Core is placed in real mode and
the registers listed in Table 5-1 are set to their initialized
values. RESET# invalidates and disables the CPU cache,
Register Register Name
EAX Accumulator
EBX Base
ECX Count
EDX Data
EBP Base Pointer
ESI Source Index
EDI Destination Index
ESP Stack Pointer
EFLAGS Extended Flags
EIP Instruction Pointer
ES Extra Segment
CS Code Segment
SS Stack Segment
DS Data Segment
FS Extra Segment
GS Extra Segment
IDTR Interrupt Descriptor Table Register
GDTR Global Descriptor Table Register
LDTR Local Descriptor Table Register
TR Task Register
CR0 Control Register 0
CR2 Control Register 2
CR3 Control Register 3
CR4 Control Register 4
Note 1. x = Undefined value.
AMD Geode™ LX Processors Data Book

Table 5-1. Initialized Core Register Controls

Initialized Contents
(Note 1)
xxxxxxxxh
xxxxxxxxh
xxxxxxxxh
xxxx 04 [DIR0]h
xxxxxxxxh
xxxxxxxxh
xxxxxxxxh
xxxxxxxxh
00000002h
0000FFF0h
0000h
F000h
0000h
0000h
0000h
0000h
Base = 0, Limit = 3FFh
xxxxxxxxh
xxxxh
xxxxh
60000010h
xxxxxxxxh
xxxxxxxxh
00000000h

5.0CPU Core

and turns off paging. When RESET# is asserted, the CPU
terminates all local bus activity and all internal execution.
While RESET# is asserted, the internal pipeline is flushed
and no instruction execution or bus activity occurs.
Approximately 150 to 250 external clock cycles after
RESET# is de-asserted, the processor begins executing
instructions at the top of physical memory (address location
FFFFFFF0h). The actual number of clock cycles depends
on the clock scaling in use. Also, before execution begins,
20
an additional 2 clock cycles are needed when self-test is
requested.
Typically, an intersegment jump is placed at FFFFFFF0h.
This instruction forces the processor to begin execution in
the lowest 1 MB of address space. Table 5-1 lists the CPU
Core registers and illustrates how they are initialized.
Comments
00000000h indicates self-test passed.
DIR0 = Device ID
See Table 5-4 on page 93 for bit definitions.
Base address set to 00000000h. Limit set to FFFFh.
Base address set to FFFF0000h. Limit set to FFFFh.
Base address set to 00000000h. Limit set to FFFFh.
Base address set to 00000000h. Limit set to FFFFh.
Base address set to 00000000h. Limit set to FFFFh.
Base address set to 00000000h. Limit set to FFFFh.
See Table 5-10 on page 96 for bit descriptions.
See Table 5-9 on page 96 for bit descriptions.
See Table 5-8 on page 96 for bit descriptions.
See Table 5-7 on page 96 for bit descriptions.
33234H
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